Imaging Device Gate Electrode Overlap for Parasitic Capacitance
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Solution Overview
Problem
Solid-state imaging devices using organic photoelectric conversion layers face challenges in achieving a wide dynamic range while minimizing leakage currents, due to increased parasitic capacitance and limited dynamic range of the charge storage capacitance.
Innovation Solution
The design includes a semiconductor substrate with a photoelectric converter and transistors, where the reset transistor is positioned above the semiconductor substrate, with a gate electrode partially overlapping and partially not overlapping the pixel electrode, reducing parasitic capacitance and allowing for a wider dynamic range and minimized leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode completely overlaps the pixel electrode to improve transistor performance, then the transistor operation is enhanced, but the parasitic capacitance increases reducing the dynamic range
Solution Approach 1:
The gate electrode is designed with non-uniform overlapping characteristics: a first region overlaps the pixel electrode to ensure proper transistor operation, while a second region extends beyond the pixel electrode to reduce parasitic capacitance. This local differentiation allows the gate electrode to simultaneously achieve reliable transistor operation and minimize harmful parasitic effects.
Solution Approach 2:
The gate electrode is segmented into functionally distinct regions: a first region that overlaps the pixel electrode for transistor control, and a second region that extends beyond to reduce parasitic capacitance. This segmentation allows each region to optimize its specific function without compromising the other.
2Adaptability or versatility
If the charge storage capacitance is increased to expand the dynamic range, then the dynamic range improves, but the leakage current increases reducing the imaging performance
Solution Approach 1:
An insulating layer is introduced as an intermediary between the pixel electrode and the gate electrode. This insulating layer acts as a mediator that allows the gate electrode to be positioned closer to the pixel electrode for better transistor control while preventing direct contact that would increase parasitic capacitance and leakage current, thus enabling wider dynamic range without compromising imaging performance.
3Object-generated harmful factors
If the insulating layer thickness is increased to reduce parasitic capacitance, then the parasitic capacitance decreases, but the transistor performance deteriorates
Solution Approach 1:
The insulating layer is positioned specifically in the region where the gate electrode extends beyond the pixel electrode. This localized placement allows the insulating layer to reduce parasitic capacitance in the critical overlapping region while maintaining thinner insulating layer thickness in other regions to preserve transistor performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces parasitic capacitance, enabling a wider dynamic range and lower leakage currents, allowing for improved imaging performance while minimizing the thickness of insulating layers and maintaining circuit performance.
Implementation Method 1
a photoelectric converter that includes a first electrode, a second electrode and a photoelectric conversion layer sandwiched between the first electrode and the second electrode, the photoelectric converter being located above a surface of the semiconductor substrate and converting incident light into electric charges
Data Source
AI summary
An imaging device including a semiconductor substrate; and a pixel. The pixel includes a photoelectric converter having a first electrode, a second electrode and a photoelectric conversion layer sandwiched between the first electrode and the second electrode, the photoelectric converter located above a surface of the semiconductor substrate; a first transistor that includes a part of the semiconductor substrate and detects electric charges; and a second transistor that includes a gate electrode and initializes a voltage of the first electrode. The first electrode, the second transistor, and the first transistor are arranged in that order toward the semiconductor substrate from the first electrode in cross sectional view, and when viewed from the direction normal to the surface of the semiconductor substrate, a part of the gate electrode overlaps the first electrode, and another part of the gate electrode does not overlap the first electrode.