Trap Rich Layer Formation for SOI RF Circuits
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Solution Overview
Problem
High resistivity substrates used in SOI technology to reduce cross talk in RF communication circuits are susceptible to parasitic surface conduction, which degrades signal purity due to nonlinear capacitance and conduction, and trap rich layers formed before active layer processing are prone to thermal degradation during high temperature processing.
Innovation Solution
A layer transferred structure with a trap rich layer introduced after active layer processing is complete, significantly increasing the separation between the substrate and active layer, and forming the trap rich layer in the handle wafer to minimize thermal degradation and preserve its efficacy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a trap rich layer is formed before active layer processing, then parasitic surface conduction is inhibited, but the trap rich layer undergoes thermal degradation during high temperature processing
Solution Approach 1:
The patent applies preliminary action by forming the trap rich layer in the handle wafer before bonding, but positioning it such that it will be thermally isolated from the active layer during subsequent high temperature processing. The trap rich layer is created in the handle wafer substrate before bonding to the active layer, and the insulator layer is formed between the trap rich layer and the active layer, providing thermal isolation during processing while maintaining the trap rich layer's position to inhibit parasitic surface conduction.
Solution Approach 2:
The insulator layer serves as an intermediary between the trap rich layer and the active layer. This insulator layer is formed between the trap rich layer and the active layer after bonding, providing both electrical isolation and thermal protection to the trap rich layer during high temperature processing, while still allowing the trap rich layer to function in inhibiting parasitic surface conduction at the handle wafer interface.
2Reliability
If the substrate is separated from the active layer, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor structure into distinct functional layers: the handle wafer containing the trap rich layer, the insulator layer, and the active layer. This segmentation creates physical separation between the substrate and the active layer, reducing parasitic capacitance while organizing the complexity into manageable, functionally distinct segments that can be processed and integrated systematically.
Solution Approach 2:
The patent utilizes dimensional separation by increasing the vertical distance between the substrate (handle wafer) and the active layer through the introduction of the insulator layer and the trap rich layer structure. This dimensional change in the vertical direction achieves parasitic capacitance reduction without requiring lateral complexity, effectively using the third dimension (depth/height) to solve the problem.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively inhibits parasitic surface conduction and enhances RF performance by maintaining the integrity of the trap rich layer, reducing nonlinear capacitance, and minimizing manufacturing defects, thereby improving signal purity and device performance.
Implementation Method 1
a trap rich layer introduced after the formation of the active layer... effectively inhibits parasitic surface conduction
Data Source
AI summary
A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.