Buried Gate Electrodes via Self-Aligned Double Patterning
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Solution Overview
Problem
As semiconductor devices become more integrated, device characteristics such as threshold voltages and refresh characteristics degrade due to shortened channel lengths, and buried channels are employed to alleviate these issues, but existing methods face challenges in effectively forming buried gate electrodes and isolation patterns with improved margin and reduced fabrication steps.
Innovation Solution
The use of self-aligned double patterning to simultaneously form gate electrodes and isolation patterns with conductive and capping layers, where the conductive layers are completely below the substrate surface and the capping layers cover the conductive layers, using materials like TiN, TiSi, poly-silicon, silicon oxide, silicon nitride, and silicon oxynitride, to improve margin and reduce fabrication steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single patterning is used to form gate electrodes and isolation patterns, then fabrication steps are simpler, but manufacturing precision and alignment are degraded
Solution Approach 1:
The patterning process is divided into two separate steps: first forming mandrels with initial pattern, then forming patterned spacers on the mandrels. This segmentation allows each step to be optimized independently, achieving higher precision isolation patterns and gate electrodes through the second patterning step while maintaining manageable process complexity
Solution Approach 2:
Mandrels are formed in advance as preliminary structures that define the initial pattern. These mandrels serve as templates for subsequent spacer formation, enabling precise positioning of isolation patterns and gate electrodes before the final etching step
2Productivity
If channel length is shortened to increase device integration, then device density increases, but device characteristics such as threshold voltage and refresh characteristics degrade
Solution Approach 1:
The gate electrode is extended into the third dimension by forming it as a buried structure beneath the active region surface. This vertical dimensionality change allows the gate to maintain effective control over the channel even when the horizontal channel length is shortened, thereby preserving device characteristics while enabling higher integration density
Solution Approach 2:
The buried gate electrode is nested within the substrate beneath the active region, with the gate insulating layer surrounding the conductive layer. This nested configuration allows the gate structure to occupy vertical space without interfering with surface-level device operations, maintaining electrical characteristics while enabling compact horizontal layout
3Reliability
If buried gate electrodes are formed to improve device characteristics, then threshold voltage and refresh characteristics are improved, but fabrication complexity increases
Solution Approach 1:
The formation of buried gate electrodes and isolation patterns is merged into a single integrated process flow. Both structures are created simultaneously through the same mandrel formation and spacer deposition steps, eliminating the need for separate fabrication sequences and reducing overall process complexity despite the advanced device architecture
Solution Approach 2:
The patterned spacers serve multiple functions: they define the isolation patterns, define the gate electrode positions, and serve as etch masks for creating both structures. This multi-functionality reduces the number of dedicated process steps needed while maintaining precise control over both buried gate and isolation feature formation
Data Source
AI summary
A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, and a plurality of buried gate electrodes between a pair of the isolations, wherein each of the buried gate electrodes and the isolations includes a conductive layer and a capping layer.