High-K Metal-Insulator-Metal Capacitor Vertical Sidewall Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 3-plate MIM capacitors require complex fabrication processes with multiple masks and lithography, leading to high manufacturing costs and limited chip horizontal area, which restricts performance and scaling.
Innovation Solution
A single patterning process is used to form the core plate portions of a 3-plate MIM capacitor, utilizing both horizontal and vertical surfaces to increase density and efficiency, with a high-k dielectric material layer surrounding the metal plates and a liner metal layer on sidewall surfaces, allowing for minimal disruption to typical BEOL processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3-plate MIM capacitor fabrication is used with multiple masks and lithography, then capacitor performance is improved, but manufacturing cost increases and device complexity increases
Solution Approach 1:
The patent combines multiple capacitor plate formations into a single lithography and etching process. The single pattern creates a cavity where the first and second metal plates are formed simultaneously on opposing sidewalls, eliminating the need for separate masking and etching steps for each plate, thus reducing manufacturing complexity while maintaining performance
Solution Approach 2:
The invention transitions from horizontal capacitor plate arrangements to vertical sidewall-mounted plates. By utilizing the vertical sidewalls of a single cavity rather than horizontal layers, the patent achieves 3-plate functionality with reduced footprint and simplified processing, effectively using the third dimension to resolve the contradiction
2Reliability
If conventional 3-plate MIM capacitor structure is used, then capacitor performance is improved, but chip horizontal area is reduced
Solution Approach 1:
The patent moves capacitor plates from horizontal arrangement to vertical arrangement on cavity sidewalls. This dimensional transition allows the capacitor to utilize vertical space rather than horizontal chip area, achieving high performance while conserving valuable horizontal real estate on the chip
Solution Approach 2:
The first and second metal plates are nested within the same cavity structure, with both plates formed on the sidewalls of a single etched feature. This nesting approach allows multiple capacitor elements to share the same horizontal footprint, effectively reducing the area required per capacitor while maintaining performance
3Ease of manufacture
If single patterning process is used to form core plate portions, then manufacturing cost is reduced and chip density is enhanced, but device complexity increases
Solution Approach 1:
The single pattern is segmented to form multiple functional regions simultaneously. The lithography pattern creates a cavity where different sidewall regions will form different metal plates, and the high-k dielectric is selectively positioned to form capacitor structures. This segmentation allows one pattern to accomplish what previously required multiple patterns
Solution Approach 2:
The single lithography pattern serves multiple functions: it defines the cavity geometry, positions both metal plates on opposing sidewalls, and establishes the footprint for high-k dielectric deposition. This multi-functionality of a single pattern reduces manufacturing steps while the resulting structure's complexity is managed through systematic material deposition sequences
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and enhances chip density by enabling the use of vertical surfaces for capacitor formation, resulting in improved performance and scalability without the need for additional masks or complex etching processes.
Implementation Method 1
a layer of high-k dielectric material continuously surrounding the center metal fill region on side and bottom surfaces of the center metal fill region, the high-k dielectric material layer serving as a plate separation dielectric for the MIM capacitor
Implementation Method 2
a layer of liner metal lining sidewall surfaces of the cavity in the at least one intermediate BEOL layer, the layer of liner metal contacting an outer surface of the layer of high-k dielectric material
Data Source
AI summary
A metal-insulator-metal (MIM) capacitor, includes a cross-sectional view: a first metal plate; a second metal plate; a third metal plate; and a layer of high-k material contacting the first metal plate, the second metal plate, and the third metal plate.