3D Semiconductor Memory Vertical Contact Wiring
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Solution Overview
Problem
In semiconductor memory devices with resistive change elements, the increase in chip size due to the need for additional wirings and transistors to connect divided word lines poses a challenge, especially when stacking layers, as it complicates the electrical connections and increases the overall size of the memory chip.
Innovation Solution
The semiconductor memory device employs a structure where word lines are arranged in a cross-point configuration with resistive change elements, using contacts that pass through spaces between word lines at different levels to connect to driving circuits, thereby eliminating the need for dividing word lines and reducing the chip size by avoiding unnecessary wiring and transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If word lines are divided and additional wirings are added to connect them, then electrical connection reliability is improved, but chip size increases
Solution Approach 1:
The patent transitions from planar wiring connections to three-dimensional vertical connections by having contacts extend through multiple layers. Word lines at different levels (first level and second level) are connected via contacts that pass through intermediate structures, enabling electrical connection in the vertical dimension rather than requiring additional lateral wirings.
2Adaptability or versatility
If additional transistors are added to drive divided word lines, then word line driving capability is improved, but device complexity increases
Solution Approach 1:
The patent enables a single transistor to drive word lines at multiple levels through the use of vertically extending contacts. The contact structure serves multiple functions by simultaneously providing electrical connection for word lines at the first level and second level, eliminating the need for separate transistors for each word line level.
3Quantity of substance
If more layers are stacked, then memory capacity is improved, but wiring resistance increases causing voltage drop
Solution Approach 1:
The patent addresses voltage drop in stacked layers by implementing vertical contacts that provide direct electrical pathways through the intermediate structures. This three-dimensional connection method reduces the effective resistance compared to lateral wiring paths that would traverse through multiple layers, thereby minimizing voltage drop while maintaining high memory capacity.
Data Source
AI summary
A semiconductor memory device of an embodiment has stacked semiconductor memories, each semiconductor memory including first lines intersecting with second lines, and resistive change elements each disposed between one of the first lines and one of the second lines. In two of the semiconductor memories adjacent to each other in the stacking direction, either two of the first lines or two of the second lines are disposed along and in contact with each other. A first contact electrically connected to the second line of the uppermost semiconductor memory passes through a region between the second lines of each of the semiconductor memories located below the uppermost semiconductor memory, and a second contact electrically connected to the second line of each of the semiconductor memories located at an intermediate level passes through a region between the second lines of each of the semiconductor memories located below the intermediate level.