Boundary Scan Chain for 3D Stacked Memory Testing
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Solution Overview
Problem
Testing of 3D stacked memory devices is costly and inefficient due to the need for significant hardware to access I/O connections, which occupies limited space and increases manufacturing costs, and existing scan chain technologies are complex and primarily designed for chip-to-chip interconnect testing.
Innovation Solution
A lightweight boundary scan chain with a single latch per I/O cell and reduced command decoding logic, supporting both serial and parallel input/output operations, allowing for efficient testing of TSV connections within the memory stack and between the stack and the SoC or memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scan chain hardware is used for testing I/O connections in stacked memory, then testing capability is achieved, but hardware space consumption increases and manufacturing cost increases
Solution Approach 1:
The patent extracts only the essential boundary scan chain components (latches and multiplexers) at the I/O cells, eliminating the need for complex scan chain infrastructure throughout the entire memory array. This selective extraction maintains testing capability while dramatically reducing hardware space consumption.
Solution Approach 2:
The scan chain is segmented into discrete boundary elements located only at the I/O cells rather than being continuously distributed throughout the device. This segmentation allows testing functionality to be isolated to specific locations, reducing overall hardware requirements while maintaining comprehensive testing capability.
2Reliability
If conventional scan chain hardware is used for testing I/O connections in stacked memory, then testing capability is achieved, but manufacturing cost increases
Solution Approach 1:
By extracting only the necessary boundary scan components and eliminating redundant scan chain infrastructure, the patent reduces material costs and manufacturing complexity. The simplified architecture requires fewer transistors and interconnects, directly lowering manufacturing expenses while preserving essential testing functionality.
3Adaptability or versatility
If existing scan chain technology is used, then chip-to-chip interconnect testing is supported, but the technology becomes complex and is not optimized for within-stack or stack-to-SoC testing
Solution Approach 1:
The boundary scan chain implements local quality by placing specialized testing elements (latches and multiplexers) specifically at the I/O cells where they are most needed for boundary scanning. This localized approach provides optimized testing capability for within-stack and stack-to-SoC connections without requiring complex scan chain infrastructure throughout the entire device.
Solution Approach 2:
The boundary scan chain elements at I/O cells serve multiple functions: they enable serial scan testing, support parallel data transfer, and facilitate both within-stack testing and stack-to-SoC verification. This multi-functionality achieves broad testing coverage without increasing overall system complexity.
Data Source
AI summary
A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.