CMOS Image Sensor Interposer Package with Transparent Substrate
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Solution Overview
Problem
Current packaging techniques for image sensor chips, such as chip-on-board and shellcase wafer level CSP, face challenges with assembly limitations, size constraints, yield issues, and high costs due to packaging of defective chips before testing, as well as limitations in I/O connections and complex test handling in standard WLP packages.
Innovation Solution
A packaging solution involving a handler assembly with preformed electrical circuitry, an optically transparent substrate assembly with preformed electrical circuitry, and singulated image sensor chips, where each component is tested separately before integration, allowing only known good components to be used, and forming a low-profile package with improved mechanical support and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chip-on-board or shellcase wafer level CSP packaging techniques are used, then image sensor modules can be assembled, but assembly becomes increasingly difficult and costly as pixel density increases
Solution Approach 1:
The packaging process is divided into separate stages: wafer-level packaging is performed first, then the packaged wafer is singulated into individual chips, and finally the chips are mounted on the substrate. This segmentation allows each stage to be optimized independently, improving assembly reliability while maintaining ease of manufacture.
Solution Approach 2:
The image sensor chips are packaged at the wafer level before singulation, and electrical testing is performed on the packaged chips before final assembly. This preliminary packaging and testing simplifies the final assembly process by providing pre-packaged, pre-tested components that are easier to handle and install.
2Quantity of substance
If standard WLP packages are used, then wafer level packaging can be achieved, but the package area is limited to chip area which restricts I/O connections
Solution Approach 1:
The patent transitions from fan-in packaging (where I/O connections are limited to the chip area) to fan-out packaging (where the substrate extends beyond the chip area to provide additional connection points). This dimensional expansion of the package area allows for increased I/O connections while maintaining compact form factor.
3Reliability
If shellcase WLCSP technique is used, then wafer level packaging is achieved, but defective chips are packaged before testing which drives up cost
Solution Approach 1:
Electrical testing is performed on the packaged chips at the wafer level before singulation. This preliminary testing identifies defective chips early in the process, allowing them to be discarded before costly final assembly. This approach improves yield rate by ensuring only good chips are assembled, while controlling costs by avoiding waste of assembly resources on defective units.
4Productivity
If bare die packages are used, then wafer level packaging can be implemented, but test handling and assembly become complex
Solution Approach 1:
The chips are pre-packaged in a protective shellcase structure at the wafer level before singulation. This preliminary packaging provides mechanical protection and a standardized interface for handling, making the chips easier to manage during testing and assembly. The pre-packaged chips can be handled as complete units rather than fragile bare dies, simplifying test handling and improving assembly efficiency.
Data Source
AI summary
An image sensor package and method of manufacture that includes a crystalline handler with conductive elements extending therethrough, an image sensor chip disposed in a cavity of the handler, and a transparent substrate disposed over the cavity and bonded to both the handler and image sensor chip. The transparent substrate includes conductive traces that electrically connect the sensor chip's contact pads to the handler's conductive elements, so that off-chip signaling is provided by the substrate's conductive traces and the handler's conductive elements.