Dual Gate TFT Structure Preventing Electrical Shorts via Auxiliary Patterns
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Solution Overview
Problem
The existing dual-gate type TFTs in display devices face an electrical short problem due to material migration between the drain and second gate electrodes, and source and second gate electrodes, which affects the operation and image quality.
Innovation Solution
The solution involves a dual gate type TFT structure with a specific configuration including a first gate electrode, semiconductor layer, etch stopper with contact holes, drain and source electrodes, passivation layer, and a planarization layer, where the second gate electrode is electrically connected through auxiliary patterns, preventing electrical shorts by maintaining a separation between the electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a dual-gate type TFT structure is used to improve ON current property, then the mobility and switching performance are enhanced, but material migration occurs between electrodes causing electrical shorts
Solution Approach 1:
The patent introduces an auxiliary pattern as an intermediary conductive structure between the second gate electrode and the source/drain electrodes. This auxiliary pattern acts as a mediator that provides a controlled electrical connection path, preventing direct material migration and electrical shorts between the second gate electrode and source/drain electrodes while maintaining the dual-gate TFT's high ON current performance
Solution Approach 2:
The patent segments the electrical connection path by introducing auxiliary patterns that are spatially separated from the source and drain electrodes. The auxiliary pattern is divided into multiple portions (first auxiliary pattern portion and second auxiliary pattern portion) that are positioned at different locations, creating distinct connection zones that prevent direct contact and material migration between adjacent electrodes
2Device complexity
If the second gate electrode is directly connected to source and drain electrodes to simplify structure, then the device complexity is reduced, but electrical shorts occur due to material migration
Solution Approach 1:
The auxiliary pattern serves as a mediating structure that simplifies the overall device architecture by providing a built-in connection solution within the TFT structure itself, rather than requiring external wiring or complex interconnections. This intermediary structure reduces device complexity while simultaneously preventing electrical shorts
3Ease of manufacture
If the contact area between electrodes is non-uniform to ease manufacturing, then the fabrication process is simplified, but the image quality and device performance deteriorate
Solution Approach 1:
The auxiliary pattern is designed with different local configurations: the first auxiliary pattern portion is positioned adjacent to the source electrode with a first contact area, while the second auxiliary pattern portion is positioned adjacent to the drain electrode with a second contact area. This local quality differentiation allows each contact region to be optimized independently, achieving uniform contact areas that improve manufacturing precision while maintaining ease of manufacture through a relatively simple fabrication process
Data Source
AI summary
The present invention provides a display device and a dual gate type thin film transistor (TFT) structure for an electronic device. According to an embodiment, the dual gate TFT structure includes a first gate electrode formed on a substrate; a semiconductor layer formed on the first gate electrode; an insulating layer formed on the semiconductor layer, and including first, second and third contact holes therein; drain and source electrodes in contact with the semiconductor layer respectively through the first and second contact holes; a passivation layer formed on the drain electrode and the source electrode, and including a fourth contact hole therein; a planarization layer formed on the passivation layer, and including a fifth contact hole therein; and a second gate electrode formed on the planarization layer, and in electrical contact with the first gate electrode through the third, fourth and fifth contact holes.