Semiconductor Integrated Circuit Device With Vertical Power Wiring
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Solution Overview
Problem
In gate arrays, the predetermined pattern of basic cells makes it difficult to reduce the cell area, limiting the ability to make the cell area smaller compared to standard cell methods.
Innovation Solution
The semiconductor integrated circuit device incorporates a design with first and second power wirings, diffusion layers for p-channel and n-channel MOSFETs, and gate electrodes that straddle these layers, allowing for the use of space within the basic cell for other wirings and reducing the length of the basic cell by eliminating the need for power wirings within the cell, and utilizing contact portions and diffusion layers for efficient power supply and backgates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a predetermined basic cell pattern is used in gate arrays, then manufacturing efficiency is improved, but the cell area cannot be reduced below standard cell method limits
Solution Approach 1:
The patent repositions power wirings from the horizontal plane to the vertical dimension by forming them below the basic cell structure. This allows the basic cell to be shortened in the horizontal direction while power supply functionality is maintained through vertical stacking, effectively utilizing three-dimensional space to resolve the area constraint.
Solution Approach 2:
The patent embeds power wirings, diffusion layers for backgates, and contact portions within and below the basic cell structure. By nesting these supporting elements inside the cell architecture rather than placing them externally, the overall cell footprint is reduced while maintaining all necessary functionalities.
2Reliability
If power wirings are included within the basic cell, then power supply is ensured, but the basic cell length increases
Solution Approach 1:
Power wirings are moved from the horizontal plane to the vertical dimension by forming them below the basic cell. This dimensional relocation allows the basic cell length to be reduced while power supply reliability is maintained through the vertically stacked power wiring structure that extends beneath the cell.
Solution Approach 2:
The patent uses diffusion layers formed below the power wirings as backgate structures, creating functional copies that provide both power supply and backgate control. This copying approach allows the basic cell to be compact while maintaining multiple functionalities through shared structural elements.
3Adaptability or versatility
If space within the basic cell is utilized for other wirings, then wiring capability is improved, but the basic cell area is reduced
Solution Approach 1:
By forming power wirings and diffusion layers in the vertical dimension below the basic cell, the patent frees up horizontal space within the basic cell for additional wiring and circuit elements. This dimensional separation enables improved wiring capability without increasing the basic cell footprint.
Solution Approach 2:
The patent segments the basic cell structure into multiple functional layers: the upper portion contains the main circuit elements and wiring, while the lower portion contains power wirings and backgate diffusion layers. This segmentation allows independent optimization of each layer, improving overall wiring capability while maintaining compact area.
Data Source
AI summary
A semiconductor integrated circuit device includes a first power wiring that is formed on a semiconductor substrate and that extends in a first direction, a second power wiring that extends in the first direction such that the second power wiring is separated from the first power wiring, a first diffusion layer that is used for a p-channel type MOSFET and that is formed in a region between the first power wiring and the second power wiring, a second diffusion layer that is used for an n-channel type MOSFET and that is formed on a side of the second power wiring with respect to the first diffusion layer in the region between the first power wiring and the second power wiring, a first gate electrode that extends in a second direction perpendicular to the first direction and that straddles the first diffusion layer, a second gate electrode that extends in the second direction and that straddles the second diffusion layer, and a third diffusion layer for backgates that is formed below at least one of the first power wiring and the second power wiring and that is placed in a dotted manner along the first direction.