Silicon Oxynitride Mask for Planarization in Semiconductor Devices
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Solution Overview
Problem
The challenge in scaling down semiconductor memory devices, such as EEPROMs, is that conventional fabrication techniques often introduce defects, leading to degraded performance and potential device failure due to increased sensitivity at smaller sizes.
Innovation Solution
The method involves forming a silicon oxynitride mask layer to enhance lithographic precision and planarization, using it as a stop layer during etching and polishing processes, and employing ceria-based slurries for chemical mechanical polishing to maintain structural integrity and precision in forming semiconductor devices with smaller design features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication techniques are used for scaling memory devices, then manufacturing process is simpler, but device performance degrades and defects increase
Solution Approach 1:
The fabrication process is segmented into distinct stages with specialized layers: a first dielectric layer for isolation, a second dielectric layer for planarization, and a silicon oxynitride mask layer for precise patterning. Each layer serves a specific function to address performance issues at different fabrication stages.
Solution Approach 2:
The silicon oxynitride mask layer acts as an intermediary between the photoresist layer and the underlying dielectric layers. It provides a stable etch stop layer that prevents defects during etching while enabling precise lithographic patterning, thereby improving device reliability without excessive complexity.
2Productivity
If design features are reduced to increase device density, then manufacturing throughput increases, but fabrication defects increase and performance degrades
Solution Approach 1:
Different regions of the device structure receive specialized treatment through the multi-layer approach. The silicon oxynitride mask layer provides enhanced lithographic precision locally at critical patterning regions, while the dielectric layers provide local planarization and isolation where needed, maintaining manufacturing precision despite reduced feature sizes.
Solution Approach 2:
The invention changes material parameters by using silicon oxynitride with specific etch selectivity and optical properties. This material has different refractive index and etch rates compared to conventional masks, enabling better lithographic spacing and precision at reduced feature sizes while maintaining manufacturing throughput.
3Ease of manufacture
If conventional etching and deposition techniques are used, then process simplicity is maintained, but defects increase at reduced scale
Solution Approach 1:
The invention uses composite material structures: a stack of dielectric layers combined with a silicon oxynitride mask layer. This composite approach combines the simplicity of conventional deposition with enhanced performance - the silicon oxynitride provides defect reduction during etching while maintaining process compatibility with existing manufacturing equipment.
4Manufacturing precision
If lithographic spacing is improved for smaller features, then manufacturing precision increases, but process complexity increases
Solution Approach 1:
The invention extracts the lithographic precision function into a dedicated silicon oxynitride mask layer, separating it from the photoresist layer. This allows the photoresist to focus on pattern definition while the silicon oxynitride layer provides the enhanced lithographic spacing and etch stop functionality, achieving high precision without proportionally increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves lithographic spacing and manufacturing throughput, reducing defects and enhancing the reliability and performance of non-volatile memory devices by minimizing the impact of fabrication processes on smaller structures.
Implementation Method 1
planarizing the oxide material to an upper surface of silicon oxynitride mask using at least a ceria-based slurry
Implementation Method 2
etching the substrate, the first dielectric layer, and the second dielectric layer to form at least one isolation trench
Data Source
AI summary
A method for forming a semiconductor device may include forming a silicon oxynitride mask layer over a first layer. The first layer may be etched using the silicon oxynitride mask layer, to form a pattern in the first layer. The pattern may be filled with a dielectric material. The dielectric material may be planarized using a ceria-based slurry and using the silicon oxynitride mask layer as a stop layer.