Semiconductor Memory Device With Segmented Control Circuits
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Solution Overview
Problem
Existing semiconductor memory devices with three-dimensional memory cell arrays face challenges in efficiently arranging control circuits beneath the memory cell arrays to minimize chip area, particularly in stacking and arraying high-density memory cell arrays without increasing the cell array area.
Innovation Solution
The semiconductor memory device incorporates a checkerboard arrangement of first and second control circuits on the semiconductor substrate beneath the memory cell arrays, with line contact areas connecting the control circuits to the memory cell arrays, allowing for efficient selection and driving of bit lines and word lines, enabling independent control of multiple memory blocks with reduced chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If control circuits are arranged beneath memory cell arrays in conventional layouts, then memory capacity can be increased through stacking, but chip area increases due to inefficient control circuit arrangement
Solution Approach 1:
The control circuits are segmented into first and second control circuits that are separately arranged in distinct regions beneath the memory cell arrays. This segmentation allows each control circuit to be optimized for its specific function (controlling first lines or second lines) and enables more efficient spatial utilization of the chip area, reducing the overall area required for control circuits while maintaining the ability to control high-density stacked memory arrays.
Solution Approach 2:
The patent transitions from planar control circuit arrangement to a three-dimensional stacked memory architecture where control circuits are positioned beneath multiple layers of memory cell arrays. By utilizing the vertical dimension and stacking memory blocks in multiple layers, the invention achieves high memory capacity without proportionally increasing chip area, as the control circuits serve multiple stacked layers simultaneously.
2Quantity of substance
If high-density memory cell arrays are stacked three-dimensionally, then memory capacity increases, but control circuit arrangement complexity increases
Solution Approach 1:
The control functionality is segmented into specialized first and second control circuits, where each circuit is responsible for controlling a specific set of lines (first lines or second lines). This functional segmentation simplifies the control logic within each circuit and makes the overall system more manageable, as each control circuit handles a defined subset of memory lines rather than requiring a single complex control structure to manage all lines across multiple stacked arrays.
3Ease of manufacture
If conventional control circuit layouts are used beneath memory blocks, then manufacturing is straightforward, but chip area efficiency decreases
Solution Approach 1:
The control circuits are divided into first and second control circuits with distinct functions and locations. This segmentation creates a modular design that maintains manufacturing simplicity through standardized circuit blocks while achieving superior area efficiency. Each control circuit can be designed and manufactured using conventional processes, but their segmented arrangement beneath the memory arrays optimizes space utilization and reduces overall chip area compared to conventional integrated control circuit layouts.
Data Source
AI summary
A semiconductor memory device comprises a semiconductor substrate; a plurality of memory cell arrays stacked on the semiconductor substrate, each memory cell array including a plurality of first lines paralleled with each other, a plurality of second lines paralleled with each other and formed crossing the first lines, and a plurality of memory cells arranged at intersections of the first lines and the second lines, each memory cell having one end connected to the first line and the other end connected to the second line; a first control circuit provided on the semiconductor substrate immediately beneath the memory cell arrays and having one end connected to the first line to select and drive the first line; and a second control circuit provided on the semiconductor substrate immediately beneath the memory cell arrays and having one end connected to the second line to select and drive the second line.