Trench Memory Dual Control Gates Charge Retention

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Solution Overview

Problem

As semiconductor memory devices scale down, charge retention becomes increasingly difficult due to thinner dielectric layers and increased coupling between neighboring floating gates, leading to programming and read disturbances in NAND flash and other charge trapping site-based structures.

Innovation Solution

The implementation of memory cells with dual control gates, where one control gate is adjacent to the trench containing charge carrier trap sites and the other extends over the trench, mitigates disturb conditions through discrete or continuous charge carrier trapping sites on sidewalls or plugs between sidewalls, using higher-k dielectric materials for improved charge storage and isolation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If dielectric layers are made thinner to enable scaling, then device density increases, but charge retention capability deteriorates

Engineering Contradiction:
Improvedevice densityVSAvoidcharge retention capability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent employs composite dielectric materials with higher-k values to replace conventional lower-k dielectric layers. This allows the dielectric layers to be made thinner for scaling while maintaining or improving charge retention capability, as the higher-k materials provide superior electrical isolation and charge storage properties despite reduced thickness.

Inventive Principle:
Principle #40Composite materials

2Quantity of substance

If separation between floating gates is reduced to increase density, then device density improves, but coupling from neighboring floating gates increases causing programming and read disturbances

Engineering Contradiction:
Improvedevice densityVSAvoidprogramming and read disturbances
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The patent introduces higher-k dielectric materials as intermediary layers between neighboring floating gates. These dielectric layers act as mediators that reduce capacitive coupling and electrical interference between adjacent cells, thereby minimizing programming and read disturbances even when cells are closely spaced for high density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

By using composite dielectric structures with higher-k materials, the patent achieves better electrical isolation between neighboring floating gates. The enhanced dielectric properties provide superior charge confinement and reduce cross-talk, allowing cells to be placed closer together without suffering from increased coupling effects.

Inventive Principle:
Principle #40Composite materials

3Quantity of substance

If gate lengths are reduced to enable scaling, then device density increases, but fabrication difficulty increases

Engineering Contradiction:
Improvedevice densityVSAvoidfabrication difficulty
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent changes the dielectric parameter (k-value) of the materials used in the structure. By transitioning from lower-k to higher-k dielectric materials, the patent maintains effective electrical isolation and charge retention even as gate lengths are reduced for scaling. This parameter change allows continued fabrication feasibility despite smaller dimensions, as the higher-k materials provide enhanced field control and charge confinement that simplifies the fabrication process at scaled dimensions.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances charge retention and reduces programming and read disturbances, facilitating the fabrication of smaller gate lengths and maintaining high memory density with improved reliability and low power consumption.

Implementation Method 1

charge carrier trap sites in trenches

Methodology Applied
Scientific EffectCharge carrier trapping: Absorption (physical)

Implementation Method 2

higher-k dielectric materials for improved charge storage and isolation

Methodology Applied
Scientific EffectDielectric permittivity: Dielectric Permittivity

Data Source

PatentUS8284616B2Trench memory structure operation
Publication Date: 2012.10.09 MICRON TECHNOLOGY INC
  • US8284616B2 patent drawing
  • US8284616B2 patent drawing
  • US8284616B2 patent drawing

AI summary

Memory cells utilizing dielectric charge carrier trapping sites formed in trenches provide for non-volatile storage of data. The memory cells of the various embodiments have two control gates. One control gate is formed adjacent the trench containing the charge carrier trap. The other control gate has a portion formed over the trench, and, for certain embodiments, this control gate may extend into the trench. The charge carrier trapping sites may be discrete formations on a sidewall of a trench, a continuous layer extending from one sidewall to the other, or plugs extending between sidewalls.