TFT Array Substrate Etching for Electrode Edge Alignment
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Solution Overview
Problem
The existing 4Mask process for manufacturing TFT-LCD array substrates results in isotropic etching of metal thin-film layers, leading to edge shrinkage of source and drain electrodes, which affects the smooth transition with N+ contact layers, impacting TFT performance.
Innovation Solution
The method involves a four-masking process to form TFTs and pixel electrodes, with enhanced second masking to ensure the edges of N+ contact layers align smoothly with source and drain electrodes, using a gray-tone-mask process and plasma ashing to achieve precise etching, and a fourth masking process to form pixel electrodes electrically connected through holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a 4Mask process with isotropic etching is used to manufacture TFT-LCD array substrates, then manufacturing cost is reduced, but edge shrinkage of source and drain electrodes occurs, affecting TFT performance
Solution Approach 1:
The patent segments the etching process into two distinct stages: first using isotropic etching to form the basic electrode pattern, then using anisotropic etching to refine and align the edges. This segmentation allows each etching method to perform its optimal function while achieving both cost reduction and precision alignment.
Solution Approach 2:
The patent changes the etching parameters by switching from isotropic to anisotropic etching conditions. By adjusting the etching directionality parameter, the process transitions from forming the initial pattern to achieving precise edge alignment, thereby resolving the contradiction between manufacturing simplicity and precision.
2Device complexity
If isotropic etching is used in the second masking process, then the manufacturing process is simplified, but the edges of source and drain electrodes do not smoothly transition with N+ contact layers
Solution Approach 1:
The etching process is divided into two sequential steps: isotropic etching for initial pattern formation followed by anisotropic etching for edge refinement. This segmentation enables the process to maintain simplicity while achieving smooth edge transitions through the complementary action of the two etching methods.
Solution Approach 2:
The patent ensures continuous useful action by making the anisotropic etching step immediately follow the isotropic etching step without interruption. This continuous process ensures that the edge refinement occurs seamlessly on the freshly formed patterns, maintaining both process efficiency and shape precision.
3Productivity
If the second masking process uses conventional etching, then manufacturing steps are reduced, but trench length of TFT is affected, impacting performance
Solution Approach 1:
The patent changes the etching directionality parameter from isotropic to anisotropic in the second stage of the masking process. This parameter change ensures that vertical etching occurs without lateral deviation, preserving the trench length while maintaining manufacturing efficiency through the reduced step count of the 4Mask process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves TFT performance by ensuring smooth transitions and maintaining the trench length, enhancing the overall performance of the TFTs while reducing manufacturing costs.
Implementation Method 1
applying a gray-tone-mask process to expose and develop the photo-resistor layer to obtain a first photo-resistor mask
Implementation Method 2
applying a plasma ashing process to the first photo-resistor mask to obtain a second photo-resistor mask
Implementation Method 3
applying a first wet etching process to etch a portion of the metal thin-film layer that is not covered by the first photo-resistor mask
Implementation Method 4
applying a first dry etching process to etch portions of the semiconductor thin-film layer and the N+ doping thin-film layer that are not covered by the first photo-resistor mask
Data Source
AI summary
The present disclosure relates to a manufacturing method of array substrates, wherein a second masking process forming an active layer, a source electrode and a drain electrode further includes: forming a semiconductor thin-film layer, N+ doping thin-film layer, a metal thin-film layer, and a photo-resistor layer on a gate insulation layer in sequence; applying a gray-tone-mask process to expose and develop the photo-resistor layer to obtain a first photo-resistor mask; applying a first wet etching process and a first dry etching process to etch the metal thin-film layer, the semiconductor thin-film layer, and the N+ doping thin-film layer; applying a plasma ashing process to the first photo-resistor mask to obtain a second photo-resistor mask; applying a second wet etching process to etch the metal thin-film layer; and peeling off the second photo-resistor mask, applying a second dry etching process to etch the N+ doping thin-film layer. The present disclosure also relates to the array substrate formed by the above manufacturing method and the display device having the array substrate.