Insulating Layer Planarization for Nanowire Active Region Definition

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Solution Overview

Problem

The three-dimensional nature of nanowire LEDs poses challenges in fabrication, particularly in the wire bonding step where mechanical pressure can break nanowires, and conventional dry etch methods for defining the active region are inefficient, leading to smaller active regions and more process steps.

Innovation Solution

A method involving the formation of an insulating layer, such as a low temperature oxide layer, over nanowire arrays to planarize the surface and define the active region through wet etching, reducing the number of process steps and increasing the active region size, while also providing planarized bond pad areas.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If conventional dry etch methods are used to define the active region, then the active region can be defined, but the process requires multiple steps and results in smaller active region size

Engineering Contradiction:

Improveactive region sizeVSAvoidnumber of process steps

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent combines the active region definition and planarization functions into a single insulating material layer. This layer serves dual purposes: it defines the active region boundaries and provides a planar surface for subsequent processing, thereby reducing the total number of process steps while maintaining or increasing the active region area.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The insulating material layer is designed to perform multiple functions simultaneously: it acts as a boundary definition for the active region, provides mechanical support, enables planarization for wire bonding, and facilitates electrical isolation. This multi-functionality reduces process complexity while achieving larger active regions.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If wire bonding is performed on three-dimensional nanowire structures, then electrical connection can be established, but mechanical pressure causes nanowire breakage

Engineering Contradiction:

Improvenanowire integrity during bondingVSAvoidwire bonding processability

Core Design Contradiction:

ReliabilityVSEase of operation

Solution Approach 1:

The insulating material layer acts as an intermediary between the three-dimensional nanowire structure and the wire bonding process. It provides a planar, mechanically robust surface that can withstand bonding pressure, while the nanowires remain protected within the structure. This mediator enables reliable wire bonding without direct mechanical contact with the fragile nanowires.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent performs planarization by forming the insulating material layer before the wire bonding step. This preliminary action creates a mechanically stable surface that can support the subsequent bonding process, preventing nanowire breakage that would occur if bonding were attempted directly on the three-dimensional nanowire structure.

Inventive Principle:

Principle #10Preliminary action

3Ease of operation

If the insulating material layer is formed over nanowire arrays, then planarization is achieved and active region can be defined, but additional process steps are required

Engineering Contradiction:

Improvesurface planarity for bondingVSAvoidfabrication process steps

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

The insulating material layer formation process is designed to simultaneously achieve planarization and active region definition. By combining these two functions into a single layer and process step, the patent reduces the total number of fabrication steps while providing the necessary planar surface for wire bonding.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces the risk of nanowire breakage during bonding and allows for a larger active region with fewer process steps compared to conventional dry etch methods, enhancing the fabrication efficiency of nanowire LED devices.

Implementation Method 1

forming an insulating material layer over at least a portion of the plurality of nanowires such that at least a portion of the insulating material layer provides a substantially planar top surface

Methodology Applied

Scientific EffectPlanarization:

Implementation Method 2

removing a portion of the insulating material layer to define an active region of nanowires

Methodology Applied

Scientific EffectWet etching:

Data Source

PatentUS9640723B2Insulating layer for planarization and definition of the active region of a nanowire device

Publication Date: 2017.05.02 SAMSUNG ELECTRONICS CO LTD

AI summary

Various embodiments include methods of fabricating a semiconductor device that include forming a plurality of nanowires on a support, wherein each nanowire comprises a first conductivity type semiconductor core and a second conductivity type semiconductor shell over the core, forming an insulating material layer over at least a portion of the plurality of nanowires such that at least a portion of the insulating material layer provides a substantially planar top surface, removing a portion of the insulating material layer to define an active region of nanowires, and forming an electrical contact over the substantially planar top surface of the insulating material layer.