3D Memory I/O Reference Voltage Training for Signal Integrity
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Solution Overview
Problem
Conventional techniques for initializing 3D NAND flash memory devices face challenges in accurately calibrating circuitry for high-speed data communication due to process technology limitations and reliability issues, leading to significant AC timing margin loss and excessive power consumption.
Innovation Solution
A method for input/output voltage training in 3D memory devices involving setting a reference voltage value through on-die termination, performing write training, and optimizing the voltage based on read-out operations, without requiring additional ODT enable/disable commands, to enhance signal integrity and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional initialization procedures are used for 3D NAND flash memory devices, then the device can be initialized, but significant AC timing margin loss occurs and power consumption is excessive
Solution Approach 1:
The patent adjusts the reference voltage value dynamically during the initialization procedure based on the results of write and read training operations. By changing the reference voltage parameter from its default value to an optimized value determined through training, the system achieves better signal integrity and reduces power consumption while maintaining reliable data communication.
2Reliability
If conventional initialization procedures are used for 3D NAND flash memory devices, then the device can be initialized, but AC timing margin loss occurs
Solution Approach 1:
The patent modifies the reference voltage parameter during initialization through a training process that evaluates write and read operations. This parameter adjustment optimizes the timing margins by aligning the reference voltage with the actual electrical characteristics of the device, thereby improving signal communication accuracy and reducing timing losses.
3Measurement precision
If multiple initialization phases are performed including ZQ calibration and Vref DQ Calibration, then calibration accuracy is improved, but the initialization process becomes more complex
Solution Approach 1:
The patent integrates the reference voltage adjustment process into the existing initialization procedure by combining write training and read training operations. Instead of treating these as separate calibration phases, the method merges them into a unified training process that determines the optimized reference voltage value, thereby reducing procedural complexity while maintaining calibration accuracy.
Solution Approach 2:
The patent implements a feedback mechanism where the results of write training and read training operations are used to determine whether the reference voltage value needs adjustment. The system continuously monitors the training outcomes and adjusts the reference voltage accordingly, creating a closed-loop control system that simplifies the initialization process while ensuring accurate calibration.
Data Source
AI summary
Methods for input/output voltage training of a three-dimensional (3D) memory device can comprise the following operations: (1) setting a reference voltage value at an on-die termination (ODT) enabled status; (2) controlling the 3D memory device to perform a write training process; (3) determining whether a further write training process is needed; (4) in response to determining that the further write training process is needed, repeating operations (1), (2) and (3); and (5) in response to determining that the further write training process is not needed, setting the reference voltage value as an optimized reference voltage value.