3D Memory Device Horizontal Vertical Word Line Interconnections
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming horizontal and vertical word line interconnections without the use of hard masks, which complicates the manufacturing process and affects device density and performance.
Innovation Solution
A method involving the formation of a vertically alternating sequence of insulating and spacer material layers, followed by iterative non-offset and offset layer patterning steps to create stepped surfaces, allowing for the formation of terrace regions with specific stepped vertical cross-sectional profiles, enabling the integration of both horizontal and vertical word line interconnections without a hard mask.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If hard masks are used to form horizontal and vertical word line interconnections, then manufacturing precision is improved, but device complexity increases and manufacturing cost rises
Solution Approach 1:
The patent removes the hard mask layer from the manufacturing process entirely. Instead of using hard masks to define interconnection regions, the invention uses the alternating stack structure itself with selectively removed portions to directly form the horizontal and vertical word line interconnections, thereby simplifying the process while maintaining precision
Solution Approach 2:
The alternating stack structure serves multiple functions: it provides both the memory cell structure and the interconnection structure. The same alternating layers that form memory cells also form the horizontal and vertical word lines when selectively accessed, eliminating the need for separate hard mask layers and reducing overall process complexity
2Manufacturing precision
If hard masks are used for interconnection formation, then manufacturing precision is improved, but productivity decreases due to additional process steps
Solution Approach 1:
The patent combines the interconnection formation process with the existing memory structure fabrication. The alternating stack layers are formed using the same deposition and patterning processes used for memory cells, and the interconnections are created by selective removal and conductive material filling, merging multiple functions into a unified process flow that increases productivity
Solution Approach 2:
The alternating stack structure is prepared in advance with insulating and spacer material layers that are pre-configured to enable both memory cell formation and interconnection formation. This preliminary structuring allows subsequent processing steps to create both features simultaneously or in sequence without requiring additional hard mask deposition and removal steps
3Quantity of substance
If conventional patterning is used without stepped surfaces, then device density is maintained, but interconnection efficiency deteriorates
Solution Approach 1:
The patent introduces stepped surfaces that create vertical dimensionality in the interconnection structure. The alternating stack forms terraced regions with different elevation levels, allowing horizontal and vertical word lines to be accessed at different heights, which improves interconnection efficiency while maintaining high device density through the vertical stacking approach
4Ease of operation
If stepped surfaces are formed through iterative patterning, then interconnection efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The alternating stack structure self-organizes into the desired stepped configuration through the iterative patterning process. The insulating and spacer material layers automatically form the terraced regions with correct alignment due to their alternating nature and the selective removal process, reducing the need for high-precision external alignment while achieving efficient interconnections
Data Source
AI summary
A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, such that the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, iteratively performing a first set of non-offset layer patterning processing steps at least twice to form a first part of a terrace region including a set of stepped surfaces which extend in a first horizontal direction, and performing a second set of offset layer patterning processing steps to form a second part of the terrace region and to form a stepped vertical cross-sectional profile for patterned surfaces of the vertically alternating sequence along a second horizontal direction which is perpendicular to the first horizontal direction.