3D Memory Cell Word-Line Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The challenge of reducing parasitic capacitance and increasing memory cell density in semiconductor devices is hindered by structural limitations as memory cells are miniaturized.
Innovation Solution
A method involving the formation of a stack body with alternating semiconductor and sacrificial layers, followed by etching to create openings, lateral recesses, and replacing sacrificial dielectric layers with word lines, along with forming monocrystalline silicon layers and replacing sacrificial dielectric layers to form word lines, enhancing memory cell integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are miniaturized to increase net die, then memory cell density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent transitions from planar memory cell arrangement to three-dimensional vertical stacking. Multiple memory cells are stacked vertically along the depth dimension, allowing increased memory capacity and density without lateral expansion. This vertical arrangement reduces parasitic capacitance by minimizing lateral overlap between adjacent cells while maintaining high integration density.
Solution Approach 2:
The patent divides the memory device into multiple stacked memory cell levels separated by sacrificial dielectric layers. Each memory cell is segmented into distinct functional layers (active layers, word lines, bit lines) that are vertically arranged. This segmentation allows independent control and routing of each cell, reducing capacitive coupling between adjacent cells while maintaining high density.
2Quantity of substance
If three-dimensional memory cell arrangement is implemented, then memory cell density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs sacrificial semiconductor layers and sacrificial dielectric layers that are formed in advance during the stacking process. These sacrificial layers are deposited between alternating semiconductor layers before final processing. The sacrificial layers are subsequently removed through selective etching to create the final three-dimensional memory cell structure. This preliminary action simplifies the overall manufacturing process by breaking down complex 3D fabrication into sequential, manageable steps.
Solution Approach 2:
The patent uses sacrificial dielectric layers as intermediary structures during fabrication. These layers are deposited between word lines to temporarily support and define the three-dimensional cell structure. The sacrificial dielectric layers serve as placeholders and structural supports during manufacturing, enabling precise alignment and formation of vertical interconnects. After serving their purpose, they are selectively removed to complete the memory cell structure.
Data Source
AI summary
A method for fabricating a semiconductor device includes: forming a stack body by alternately stacking a plurality of semiconductor layers and a plurality of sacrificial semiconductor layers over a lower structure; forming an opening by etching the stack body; forming a plurality of active layers and a plurality of lateral recesses by etching the semiconductor layers and the sacrificial semiconductor layers through the opening; forming sacrificial dielectric layers partially filling the lateral recesses and contacting the active layers; and replacing the sacrificial dielectric layers with word lines.