Digital Storage TRIZ Cases

A switched voltage multiplier and regulator keep a bandgap reference precise at 0.4-1.0 V while improving PSRR for power-on-reset and voltage monitoring.

A DDR PHY layout uses central PLL placement, adjacent power switches, and decoupling capacitors to cut area, IR drop, and clock jitter.

Dynamic phase interpolation keeps data and strobe signals aligned during operation, reducing memory write errors under voltage and temperature shifts.

Sub-bank sharing lets one IO bank support multiple external memory interfaces, increasing flexibility while reducing IC die size and cost.

Selective edge equalization changes drive strength only where needed, improving multi-level memory signal quality without raising power.

Embedding pDBI within PAM3 sequence data removes separate DBI lanes, cutting power use while improving pin efficiency.

Dual-loop clock delay scheduling aligns data and DQS timing across power-voltage shifts to prevent capture faults and cut memory power use.

An assist circuit applies temporary negative bit-line voltage and lowers inverter supply to improve SRAM write capability with less power.

Bit line voltage compensation and dummy conductances help analog neural computation keep accuracy despite high output currents and ADC sensing.

Shifted via placement and stacked wiring in an output buffer cut data I/O capacitance, improving transfer rate and lowering current use.

Separate input and output ports let memory devices read and write concurrently, cutting turnaround delay and simplifying scheduling logic.

Dummy conductances and voltage sensing offset ADC-related voltage drop in CIM neural arrays, preserving accuracy with low power.

Alternating fast and dense SRAM rows with cross-coupled multiplexers cut silicon area while keeping adjacent column read performance balanced.

Different voltage domains across cache levels help monolithic logic dies fit more SRAM within die-area limits while reducing parasitic interference.

Adaptive sample-and-hold and comparator control matches neural computation precision while avoiding fixed ADC and DAC power waste.

Separate DDR4/DDR5 and LPDDR5 input paths with a hybrid cascode stage raise receiver bandwidth while handling different signal swings.

A three-stage receiver boosts high-speed gain, limits output loading, and corrects duty cycle errors across storage memory interfaces.

Complementary delay circuits use a common bias to synchronize internal memory operations while reducing delay-circuit area.

Magnetoresistive memory with integrated logic, MUX, and tri-gate hardens FPGA configuration against radiation while enabling readback and lower power.

Address comparison logic suppresses repeated memory reads and retrieves data from GIO latches to cut active-mode power without slowing access.

Switching between distorted read clocks and an internal clock improves memory data latching accuracy while avoiding unnecessary power use.

Sequential calibration codes and voltage equalization cut offset calibration time in a semiconductor memory data input buffer.

A compensation circuit corrects current mismatch and parasitic capacitance in semiconductor memory paths to improve data accuracy and speed.

A variable-impedance feedback AC-coupled clock buffer cuts duty cycle recovery time and supports 200 MHz to 10 GHz operation without extra power or area.

Parallel summer and double-tail latch feedback paths cut DFE loop delay, improving inter-symbol interference correction in high-speed memory links.

Offset clock signals compensate amplifier propagation delays so multi-level data is sampled near symbol centers for more accurate decoding.

Sequential multi-phase clocking cuts driver count and signal toggling, enabling faster memory data output with lower power.

Shunted bit lines and regulated common nodes suppress IR drops in memory arrays, improving MAC accuracy and current measurement.

A TCAM cell layout places a match cell between equal-height storage cells to speed parallel search while lowering dynamic power.

Temperature-adjusted clock generation stabilizes DRAM command delays so ECS and scrub timing conditions remain accurate across thermal changes.

A shared holding transistor lets paired sub word lines use one driver path, cutting word-line layout area without losing control reliability.

Adjustable delay on word line edges compensates voltage swing differences while preserving pulse width in dense memory circuits.

A driving circuit reduces input clock slew to prevent early reset and internal clock generation failure under PVT variation.

A two-flip-flop XOR synchronizer cuts clock-domain crossing latency to one source clock cycle while preserving reliable pulse transfer.

Shared delay ALUs and clock gating cut unnecessary register activity, lowering power in reconfigurable signal processing circuits.

Time-multiplexed ADC sharing across CAP-RAM macros cuts power and area while preserving sampling precision and neural compute efficiency.

A current-mirror TIA for crossbar circuits avoids feedback-resistor instability, keeping output voltage stable under capacitive loading and current variation.

Parallel duty cycle monitoring of data and read clocks cuts memory clock training time while correcting read clock offset and duty error.

Aging-aware delay chains widen the SRAM bit-line pre-charge window under BTI, preserving double-pumped access speed and reliability.

Partitioning FPGA logic tiles into virtual arrays enables independent clocks, shared or separate I/O, and merged bitstreams for flexible resource use.

Feed-forward gain adjustment and digital delay overcompensation reduce power supply-induced jitter and improve high-speed data reception.

A triple-gate feedback memory cell merges logic and storage in CMOS, cutting transistor count, power use, and data-transfer delay.

MOS transistors and switch circuits raise capacitance in a slew rate control circuit to delay signal edges without increasing circuit size.

Sub-bank sharing lets one I/O bank support multiple memory interfaces, increasing flexibility while reducing die size and system footprint.

A TCAM cell uses GAA transistors and a central match cell layout to maintain fast parallel search while reducing dynamic power.

A 1T-2P PCM bit circuit uses a CMOS inverter to isolate high logic voltage, preventing unintended phase changes and data loss.

Delay elements and OR-based multiplexing let adjacent superconducting memory cells share output paths, raising bit density with lower circuit overhead.

Per-line read-voltage training and duty adjustment compensate swing deviations across data lines, preserving valid window margin at high speed.

Power-up circuitry presets switch interconnect multiplexers to a common polarity, preventing contention and metastability before configuration.

A dual-voltage wordline predecoder uses NANDed row address and internal clock signals to cut memory power while limiting timing skew.