Memory Data Processing Circuit With Compensation for Signal Mismatch

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Solution Overview

Problem

Semiconductor memory circuits are prone to deviations due to manufacturing processes and design variations, leading to data transmission errors and reduced data processing speed.

Innovation Solution

A circuitry comprising a receiving circuit, compensation circuit, and processing circuit is employed to determine and compensate data signals, reducing current mismatch and parasitic capacitance, thereby improving output accuracy and processing speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If semiconductor memory circuits are designed with standard manufacturing processes, then device complexity is controlled, but manufacturing deviations cause data transmission errors reducing reliability

Engineering Contradiction:
Improvedata transmission accuracyVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A compensation circuit is introduced as an intermediary component between the receiving circuit and processing circuit. This compensation circuit generates compensation signals to counteract the effects of manufacturing deviations and parasitic capacitance, thereby improving data transmission accuracy without requiring complete redesign of the entire memory circuit.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent adjusts circuit parameters by introducing compensation signals that dynamically modify the operating characteristics of the processing circuit. By changing parameters such as signal timing and voltage levels through compensation, the system adapts to manufacturing variations and maintains reliable data transmission.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If compensation circuits are added to reduce current mismatch, then output accuracy improves, but device complexity increases

Engineering Contradiction:
Improveoutput signal accuracyVSAvoidcircuit component quantity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The compensation circuit performs preliminary correction of signal deviations before the data reaches the processing circuit. By pre-compensating for expected errors from parasitic capacitance and manufacturing variations, the system achieves higher output accuracy without requiring complex error correction after processing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The compensation circuit uses feedback mechanisms to detect and correct current mismatch and signal deviations. By continuously monitoring the signal conditions and adjusting compensation signals accordingly, the system maintains high output accuracy while keeping the compensation circuit structure relatively simple.

Inventive Principle:
Principle #23Feedback

3Speed

If parasitic capacitance between nodes is reduced through design adjustment, then high-speed characteristics improve, but manufacturing precision requirements increase

Engineering Contradiction:
Improvedata processing speedVSAvoidnode composition precision
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent extracts and separates the compensation function into a dedicated compensation circuit with specific nodes (first compensation node and second compensation node). By isolating the compensation functionality from the main data processing path, the design reduces parasitic capacitance in critical signal paths while maintaining manufacturing feasibility through standardized circuit structures.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS12518801B2Circuitry and method for processing data, and semiconductor memory
Publication Date: 2026.01.06 CHANGXIN MEMORY TECH INC
  • US12518801B2 patent drawing
  • US12518801B2 patent drawing
  • US12518801B2 patent drawing

AI summary

A circuitry for processing data includes a receiving circuit, a compensation circuit and a processing circuit. The receiving circuit is configured to receive a data signal, and determine a first node signal according to the data signal. The compensation circuit is configured to receive an initial compensation signal, and determine a target compensation signal according to the initial compensation signal. The processing circuit is configured to output a target data signal according to the first node signal and the target compensation signal. A method for processing data and a semiconductor memory are also provided.