Programmable Signal Processing Circuit With Shared Delays and Clock Gating
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Solution Overview
Problem
Programmable circuits like FPGAs suffer from high power consumption due to redundant processing and inefficient use of delay elements compared to ASICs, particularly in implementing operations requiring multiple delay amounts.
Innovation Solution
A programmable signal processing apparatus with a combination of first and second type ALUs, including selection and delay circuits, and a clock gate control circuit to manage clock signal supply, allowing flexible configuration and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a programmable circuit uses a coarse-grained configuration with large block ALUs, then area efficiency is improved compared to fine-grained configurations, but power consumption increases due to redundant processing and inability to share delay elements
Solution Approach 1:
The delay circuit is designed to be shared across multiple ALUs, allowing a single delay element to serve multiple processing units. This universal delay resource eliminates redundant delay elements in each ALU, reducing overall power consumption while maintaining area efficiency through the coarse-grained architecture.
Solution Approach 2:
The patent merges the delay functionality from individual ALU blocks into a separate, shared delay circuit that can be accessed by multiple ALUs. This combining of delay resources across the programmable circuit reduces the total number of delay elements needed, thereby lowering power consumption while preserving the area-efficient coarse-grained structure.
2Adaptability or versatility
If a programmable circuit implements multiple processing circuits using pre-designed ALUs, then flexibility and reconfigurability are improved, but power consumption increases due to redundant processing compared to specialized ASICs
Solution Approach 1:
The shared delay circuit serves multiple ALUs that can be configured for different processing functions. This universal delay resource supports various reconfigurable processing circuits without requiring each ALU to have its own dedicated delay elements, reducing power consumption while maintaining high adaptability and reconfigurability.
Solution Approach 2:
The programmable circuit allows dynamic reconfiguration of ALU functions and connections through configuration data, while the delay circuit adapts to serve different processing needs. This dynamic flexibility enables the circuit to optimize power usage by activating only the necessary delay elements for the current processing task, rather than continuously powering all delay elements as in fixed ASIC designs.
3Speed
If each ALU includes its own delay circuit, then processing independence and speed are improved, but power consumption increases due to simultaneous operation of multiple delay circuits
Solution Approach 1:
The shared delay circuit maintains continuous availability of delay functionality for multiple ALUs through efficient resource management. By allowing multiple ALUs to access the same delay elements in a coordinated manner, the system maintains processing speed and throughput while avoiding the power consumption penalty of having all delay circuits operate simultaneously and independently.
Data Source
AI summary
A programmable signal processing apparatus comprises a plurality of ALUs and a control unit that performs control for configuring a targeted circuit based on received information. The plurality of ALUs include a first type of ALU with one input and multiple outputs and a second type of ALU with two inputs and one output. The first type of ALU delays input data and outputs a plurality of pieces of data with different delay amounts. The second type of ALU generates one or two delayed data and performs an operation on the one or two data. The second ALU does not delay the one or two data in a state where supply of a clock signal to a plurality of registers in the second ALU is cut off.