Triple-Gate Logic-in-Memory Cell for Reconfigurable CMOS Logic
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Solution Overview
Problem
Conventional von Neumann-based computer systems face bottlenecks due to the separation of processor and memory, leading to inefficiencies in data processing speed and power consumption, especially in data-intensive applications like 5G communication and AI, and existing logic-in-memory technologies struggle with high power consumption, complex manufacturing, and low integration.
Innovation Solution
A reconfigurable logic-in-memory cell using triple-gate feedback memory elements fabricated with a CMOS process, capable of performing all basic logical operations and storing operation results, utilizing a positive feedback loop for channel-type variable characteristics to enhance processing speed and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic-in-memory technology is implemented using conventional volatile memory elements (SRAM, DRAM), then memory function is achieved, but a large number of transistors are required resulting in large area and high power consumption
Solution Approach 1:
The patent merges the logic operation function and memory function into a single integrated cell structure. The triple-gate feedback memory element simultaneously performs logical operations (AND, OR, NOT, NAND, NOR, XOR, XNOR) and stores the results, eliminating the need for separate logic circuits and memory cells. This integration reduces the overall transistor count while maintaining both functional requirements.
Solution Approach 2:
The triple-gate feedback memory element is designed as a universal component that can perform multiple logic operations and memory storage functions. By configuring the three gates (control gate, first programming gate, second programming gate) in different modes, a single cell can implement various boolean operations and retain data, making it a multi-functional element that replaces multiple specialized components.
2Reliability
If logic-in-memory technology is implemented using non-volatile memory elements (ReRAM, MRAM, PCRAM), then memory function with data retention is achieved, but a complex manufacturing process is required due to non-silicon materials
Solution Approach 1:
The patent changes the operational parameters of standard silicon-based CMOS transistors to achieve non-volatile memory functionality. By applying specific voltages to the three gates and utilizing the feedback mechanism, the cell can enter metastable states that retain data without power. This approach achieves non-volatile memory behavior using conventional silicon materials and CMOS fabrication processes, avoiding the need for complex non-silicon material deposition and processing.
3Adaptability or versatility
If conventional logic-in-memory cells are designed, then some logic operations are implemented, but not all basic CMOS logic operations can be performed in one cell requiring individual circuitry for each operation
Solution Approach 1:
The triple-gate feedback memory element serves as a universal logic unit capable of performing all basic CMOS logic operations (AND, OR, NOT, NAND, NOR, XOR, XNOR). By appropriately setting the control gate and programming gates, the same physical cell can be reconfigured to implement any of these logic functions, eliminating the need for separate dedicated circuits for each operation and significantly reducing wiring complexity.
Solution Approach 2:
The cell structure is designed to be dynamically reconfigurable. The three gates can be programmed in different states to change the logic function performed by the cell. This dynamic reconfiguration capability allows a single static physical structure to perform multiple different logic operations, providing versatility without requiring multiple specialized circuits.
4Ease of manufacture
If processor and memory are separated as in von Neumann architecture, then functional modularity is maintained, but data transmission time and power consumption increase due to physical separation
Solution Approach 1:
The patent merges the processor's logic function and the memory's storage function into a single integrated cell. This eliminates the physical separation between processor and memory, allowing data to be processed and stored in the same location without requiring data transmission through buses. The unified structure maintains functional modularity at the circuit level while eliminating inter-component communication delays and power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves processing speed and integration by fusing logical operation and storage functions, reducing power consumption and maintaining logical operation values without structural change, using silicon-based triple-gate feedback memory elements.
Implementation Method 1
triple-gate feedback memory elements driven by a positive feedback loop
Data Source
AI summary
The present invention relates to a reconfigurable logic-in-memory cell consisting of triple-gate feedback memory elements. The reconfigurable logic-in-memory cell according to one embodiment of the present invention includes a plurality of triple-gate feedback memory elements including a drain region, a channel region, a source region, and a gate region where first and second programming gate electrodes and a control gate electrode are formed on the channel region.