PCM Configuration Bit Circuit with Inverter Voltage Isolation
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Solution Overview
Problem
The existing configuration bit circuits in programmable logic devices using phase change memory are prone to unintended phase changes during operation due to high operating voltages exceeding the threshold voltage, leading to inaccurate signal transmission and potential data loss.
Innovation Solution
A configuration bit circuit with a 1T-2P structure incorporating a CMOS inverter and a two-terminal switching element, such as a transmission gate, is used, where the voltage applied to the phase change memory is kept below its threshold voltage to prevent phase changes, and the CMOS inverter is used to differentiate the voltage applied to the phase change memory and the inverter, ensuring stable resistance states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a voltage higher than the threshold voltage of the phase change memory is applied to operate the logic circuit, then the logic circuit can function properly, but the phase change memory may undergo unintended phase changes leading to data loss
Solution Approach 1:
The circuit is segmented into two distinct functional parts: the phase change memory cell for data storage and the CMOS inverter for logic operation. This segmentation allows the memory cell to operate at low voltage (below threshold) while the inverter handles high voltage logic operations, resolving the contradiction between operation ease and memory stability.
Solution Approach 2:
The CMOS inverter acts as an intermediary between the phase change memory cell and the external high-voltage logic circuit. It buffers and isolates the memory cell from high-voltage disturbances, allowing high-voltage logic operations without directly exposing the memory cell to threshold-exceeding voltages that would cause unintended phase changes.
2Ease of operation
If 6-T SRAM is used for configuration bit circuit, then volatile memory functionality is achieved, but excessive area is required and separate memory devices must be placed outside the FPGA
Solution Approach 1:
The invention merges the memory storage function and logic operation function into a single integrated circuit unit. The phase change memory cell and CMOS inverter are combined in one configuration bit circuit, eliminating the need for separate external memory devices and reducing overall area compared to 6-T SRAM implementations.
Solution Approach 2:
The invention changes the fundamental operating parameters of the memory cell by using phase change memory with complementary resistance states (high and low resistance) instead of volatile SRAM. This parameter change enables non-volatile storage with smaller area while maintaining the desired functionality.
3Area of stationary object
If phase change memory is used in configuration bit circuit, then area is reduced and non-volatile storage is achieved, but unintended phase changes occur during operation due to high voltage
Solution Approach 1:
The CMOS inverter is preliminarily designed to counteract the harmful effect of high voltage on the phase change memory cell. By structuring the circuit so that the inverter absorbs or blocks high-voltage effects before they reach the memory cell, the invention prevents information loss while maintaining area efficiency.
Solution Approach 2:
The CMOS inverter serves as a protective intermediary that isolates the phase change memory cell from high-voltage operations. This intermediary structure allows the circuit to benefit from both small area (via phase change memory) and high voltage operation capability without the trade-off of information loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution prevents unintended phase changes in the phase change memory, ensuring accurate signal transmission and maintaining stored information, while reducing manufacturing costs, area requirements, and enhancing security and radiation resistance.
Implementation Method 1
a first phase change memory element and a second phase change memory element connected in series between a first power source and a second power source
Data Source
AI summary
In order to provide a configuration bit circuit utilizing a phase change memory, the configuration bit circuit for a programmable logic device may include a first phase change memory element and a second phase change memory element connected in series between a first power source and a second power source, a first selection element connected to the first phase change memory element and second phase change memory element in a first direction, and a CMOS inverter connected to the first phase change memory element and second phase change memory element in a second direction and disposed between a third power source and a fourth power source.