Wordline Predecoder Timing for Dual-Voltage Memory Arrays
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Solution Overview
Problem
Semiconductor memory devices face challenges in reducing power consumption while maintaining operating margins due to voltage differences between memory cells and peripheral circuits, leading to timing skew issues.
Innovation Solution
A memory device with a dual voltage line system, where a first voltage is applied to memory cells and a second, lower voltage is applied to peripheral circuits, with a wordline predecoder generating a 'predec' signal based on both voltages to adjust operating timings, ensuring efficient power management and reducing timing skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a dual power supply scheme is used to lower the voltage provided to peripheral circuits, then power consumption is reduced, but timing skew occurs due to voltage difference between memory cells and peripheral circuits
Solution Approach 1:
The wordline predecoder generates a preliminary 'predec' signal before the row decoder operates, using both first voltage (VDDH) and second voltage (VDDL). This preliminary signal preparation at different voltage levels allows peripheral circuits to operate at lower voltage while maintaining proper timing synchronization with memory cells, thus reducing power consumption without causing timing skew
Solution Approach 2:
Different voltage levels are applied to different parts of the circuit: memory cells receive first voltage (VDDH) while peripheral circuits receive second voltage (VDDL). The wordline predecoder is designed to handle both voltage levels locally, generating control signals appropriate for each voltage domain, enabling differentiated power supply while maintaining system-wide timing coherence
2Loss of energy
If the voltage provided to memory cells is lowered to improve power efficiency, then power consumption is reduced, but the operating margin for SRAM is insufficient
Solution Approach 1:
The invention applies different voltage levels to different functional blocks: memory cells operate at higher first voltage (VDDH) to ensure sufficient operating margin and reliability, while peripheral circuits operate at lower second voltage (VDDL) to reduce power consumption. This localized voltage differentiation allows each component to operate at its optimal voltage level
Solution Approach 2:
The power supply system is segmented into multiple voltage domains: a first voltage domain (VDDH) for memory cells requiring high reliability, and a second voltage domain (VDDL) for peripheral circuits where power efficiency is prioritized. The wordline predecoder acts as an interface between these segmented voltage domains, enabling independent voltage optimization for each segment
Data Source
AI summary
A memory device and operating method of the memory device are provided. The memory device comprises a memory cell storing data based on a first voltage, a row decoder selecting a wordline of the memory cell based on the first voltage, and a wordline predecoder configured to generate a “predec” signal, which is for generating a wordline voltage to be provided to the row decoder. The wordline predecoder is driven by the first voltage and a second voltage, which is different from the first voltage, receives a row address signal, associated with selecting the wordline, and an internal clock signal associated with adjusting operating timings of elements included in the memory device. The wordline predecoder performs a NAND operation on the row address signal and the internal clock signal, and provides the “predec” signal generated based on a result of the NAND operation to the row decoder.