AC-Coupled Clock Buffer With Fast Duty Cycle Recovery
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Solution Overview
Problem
Existing AC-coupled technologies face challenges in designing an AC-coupled buffer, particularly in optimizing the duty cycle recovery time and ensuring efficient clock signal transmission, especially in a burst mode read operation, where existing solutions fail to provide an ultra-wide band performance.
Innovation Solution
The implementation of an AC-coupled buffer which reduces a duty cycle recovery time and ensures efficient clock signal transmission, especially in a burst mode read operation, where the duty cycle recovery time and ensures efficient clock signal transmission, ensuring efficient clock signal transmission, especially in a burst mode read operation, where existing solutions fail to provide an ultra-wide band performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional AC-coupled buffer is used, then the circuit structure is simple, but the duty cycle recovery time is long and ultra-wide band performance is not achieved
Solution Approach 1:
The buffer circuit is segmented into multiple parallel paths: a first buffer path for lower frequency signals and a second buffer path for higher frequency signals. Each path has its own capacitor and transistor pair, allowing independent optimization of duty cycle recovery for different frequency ranges without complicating the overall circuit structure
Solution Approach 2:
The patent implements dynamic frequency-dependent routing where the circuit automatically selects or activates different buffer paths based on the input signal frequency. This dynamic adaptation enables the circuit to achieve ultra-wide band performance with fast duty cycle recovery without requiring a completely complex redesign across the entire frequency spectrum
2Adaptability or versatility
If the buffer is designed for ultra-wide band performance, then clock frequency range is extended, but power consumption increases
Solution Approach 1:
The power consumption is segmented and distributed across multiple parallel buffer paths. Each path handles a specific frequency range, so only the necessary paths are actively consuming power for any given input signal, rather than all buffers operating simultaneously at full power
Solution Approach 2:
The circuit parameters such as capacitor values and transistor sizing are optimized differently for each frequency path. Lower frequency paths use larger capacitors while higher frequency paths use smaller capacitors, allowing each path to operate efficiently at its designated frequency range without excessive power consumption
3Adaptability or versatility
If the buffer is designed for ultra-wide band performance, then clock frequency range is extended, but circuit area increases
Solution Approach 1:
The circuit area is segmented into compact parallel modules rather than using a single large buffer. Each buffer path is designed as a compact unit with shared common elements, reducing the total area required compared to a monolithic ultra-wide band buffer design
Solution Approach 2:
The buffer paths share common circuit elements such as power supply connections, ground references, and potentially shared control logic. This multi-functionality allows the same physical infrastructure to support multiple frequency ranges, reducing redundant area consumption
Data Source
Figure 1A~1B
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AI summary
Embodiments herein relate to an alternating-current (AC)-coupled buffer in the path of a clock signal which can accommodate a wide range of clock frequencies while reducing duty cycle settling time and without increasing power consumption or area. The AC-coupled buffer includes a variable-impedance feedback element coupled between the input and output nodes of a complementary metal-oxide semiconductor (CMOS) inverter. The variable-impedance feedback element can include first and second diode-connected transistors.