Hybrid SRAM Latch Array With Balanced Fast-Slow Read Paths
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Solution Overview
Problem
Existing SRAM bit cells, particularly 6T and 8T designs, face challenges in efficiently utilizing silicon area, leading to increased costs and inefficiencies in scaling with newer technology nodes.
Innovation Solution
Implementing a hybrid SRAM design using standard cell design rules with alternating rows of high-performance and high-density bit cells, combined with multiplexer circuits and write masks, to optimize area utilization and balance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional 6T or 8T bit cells are used in SRAM, then the SRAM can store data, but the silicon area utilization is inefficient leading to increased costs
Solution Approach 1:
The SRAM array is divided into alternating rows of high-performance bit cells and high-density bit cells. This segmentation allows different portions of the array to serve different functions: some rows prioritize performance while others prioritize area efficiency, resolving the contradiction between reliable data storage and silicon area utilization.
Solution Approach 2:
Different regions of the SRAM array are assigned different cell types based on local requirements. High-performance bit cells are placed in specific rows where performance is critical, while high-density bit cells are placed in other rows where area efficiency is prioritized. This local differentiation optimizes both data storage reliability and area utilization simultaneously.
2Speed
If high-performance bit cells are used throughout the SRAM array, then data access speed is improved, but silicon area usage increases leading to higher costs
Solution Approach 1:
The array is segmented into alternating rows where odd rows contain high-performance bit cells optimized for speed, and even rows contain high-density bit cells optimized for area efficiency. This segmentation ensures that high-speed access is available where needed while maintaining overall area efficiency across the entire array.
Solution Approach 2:
High-performance characteristics are applied locally to specific rows rather than uniformly across the entire array. This allows the SRAM to achieve high data access speed in critical regions while maintaining cost-effectiveness through area-efficient cells in non-critical regions.
3Area of stationary object
If alternating rows of high-performance and high-density bit cells are implemented, then area utilization is optimized, but performance balance between adjacent bits must be maintained
Solution Approach 1:
The patent combines high-performance multiplexer circuits with high-density bit cells in alternating rows. This merging compensates for the lower performance of high-density cells by providing high-performance read/write path circuitry, thereby maintaining overall performance balance while achieving optimized area utilization.
Solution Approach 2:
High-performance multiplexer circuits act as intermediaries between the high-density bit cells and the external interface. These multiplexers compensate for the performance limitations of high-density cells, ensuring that data access performance remains balanced across adjacent bits despite the heterogeneous cell structure.
Data Source
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AI summary
A static random access memory (SRAM) includes fast SRAM bit cells and fast multiplexer circuits that are formed in a first row of fast cells in a hybrid standard cell architecture. Slow SRAM bit cells and slow multiplexer circuits are formed in a second row of slow cells. The slow multiplexer circuits provide a column output for the fast SRAM bit cells and the fast multiplexer circuits provide a column output for the slow SRAM bit cells. Thus, one SRAM column has fast bit cells and slow multiplexer stages while the adjacent SRAM column has slow bit cells and fast multiplexer stages to thereby provide an improved performance balance when reading the SRAM.