Multi-Level Signal Equalization for Lower-Power Memory Links
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently transmitting multi-level signals with high data transmission rates while minimizing power consumption and maintaining signal integrity, particularly in high-speed communication between memory controllers and devices.
Innovation Solution
A method of generating multi-level signals by selectively adjusting the drive strength of driving paths based on input data bits, performing equalization only on specific edge transitions to reduce power consumption and enhance signal characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If channel equalization is applied to all edges of multi-level signals, then signal quality is improved, but power consumption increases
Solution Approach 1:
The patent applies equalization selectively to specific edges (first edges) rather than all edges of multi-level signals. The drive strength adjustment circuit modifies drive strength based on the data bits corresponding to first edges only, leaving second edges unaffected. This localized application of equalization improves signal quality where needed while minimizing unnecessary power consumption on edges that don't require equalization.
Solution Approach 2:
The patent segments the equalization process by dividing edges into first edges and second edges based on data bit patterns. The drive strength adjustment is applied separately to first edges versus second edges, allowing selective equalization. This segmentation enables the system to focus equalization resources on specific edge types that benefit most from the process.
2Speed
If drive strength is increased for all transitions, then transition time is reduced, but power consumption increases
Solution Approach 1:
The patent adjusts drive strength locally for specific transitions (first edges) rather than uniformly increasing drive strength for all transitions. The drive strength adjustment circuit selectively modifies drive strength based on whether the transition corresponds to a first edge or second edge, reducing power consumption by avoiding unnecessary drive strength increases for second edges.
3Productivity
If multi-level signaling is used to increase data transmission rate, then communication speed is improved, but signal integrity becomes more difficult to maintain
Solution Approach 1:
The patent changes the drive strength parameter selectively for first edges to improve signal integrity. By adjusting drive strength based on data bit patterns corresponding to first edges, the system compensates for signal degradation in multi-level signaling without requiring uniform parameter changes across all signal transitions, thus maintaining signal integrity while preserving high data transmission rates.
Data Source
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AI summary
In a method of generating a multi-level signal having one of three or more voltage levels that are different from one another, input data including two or more bits is received. A drive strength of at least one of two or more driving paths is changed based on the two or more bits such that a first transition time, during which an output data signal is transitioned from a first voltage level to a second voltage level, is changed. The output data signal that is the multi-level signal is generated such that the first transition time of the output data signal is changed and a second transition time, during which the output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.