BTI-Aware SRAM Timing Circuit for Stable Bit-Line Pre-Charge
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Solution Overview
Problem
Existing double-pumped SRAM circuits suffer from Bias Temperature Instability (BTI) effects, leading to a compressed pre-charging window and performance degradation due to increased threshold voltage of transistors, which is not adequately addressed by current technologies.
Innovation Solution
Incorporating a delay chain with always-on p-type and n-type transistors coupled to the SRAM circuit, which tracks and compensates for BTI effects by adjusting the timing of clock pulses to widen the pre-charging window, using a timing controller and pre-charge circuit to manage bit line pre-charging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If double-pumped SRAM circuit is used to increase access speed, then productivity is improved, but reliability deteriorates due to BTI effects and compressed pre-charging window
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit lines before the read/write operation occurs. The pre-charge circuit activates the pre-charge signal earlier in the sequence, ensuring that bit lines are fully charged before the access operation begins, thus preventing the compressed pre-charging window problem caused by BTI effects.
Solution Approach 2:
The patent segments the clock signal into two separate non-overlapping clock phases (CLK0 and CLK1) that control different operations. This segmentation allows the pre-charging operation to be performed during one phase while the access operation occurs during the other phase, preventing timing conflicts and ensuring adequate pre-charging time despite BTI effects.
2Area of stationary object
If minimum feature size is reduced to increase integration density, then area is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent changes the timing parameters of clock signals to have non-overlapping phases with specific duty cycles. By adjusting the timing parameters rather than physical dimensions, the design achieves proper signal separation without requiring tighter feature size control, thus mitigating manufacturing precision challenges at scaled dimensions.
3Reliability
If clock pulses are delayed to widen pre-charging window, then reliability is improved, but time loss increases
Solution Approach 1:
The patent uses periodic non-overlapping clock phases that repeat in a fixed sequence. The pre-charging operation is performed during specific phases of this periodic cycle, ensuring adequate time for pre-charging without extending the overall clock cycle period, thus avoiding time loss while maintaining reliability.
Data Source
AI summary
A memory circuit includes a memory array including memory cells, wherein each of memory cells is accessible through a plurality of access lines. The memory circuit includes a delay circuit configured to receive a first clock pulse and delay the first clock pulse as a second clock pulse, wherein the second clock pulse immediately follows the first clock pulse. The memory circuit includes a logic gate configured to receive the first clock pulse and the second clock pulse, and provide a pre-charge signal for pre-charging the plurality of access lines based on the first and second clock pulses. The delay circuit includes a plurality of inverters and a plurality of transistors, such that a time difference between a first transition edge of the first clock pulse and a second transition edge of the second clock pulse is extended in accordance with an increasing age of the memory circuit.