Decision Feedback Equalizer Architecture for Faster ISI Correction
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Solution Overview
Problem
As memory device operating speeds increase, transmission paths of decision feedback equalizers (DFEs) become too slow to adequately transmit corrective signals for inter-symbol interference, leading to signal distortion and errors.
Innovation Solution
Implementing a DFE architecture with reduced loop time margin, utilizing a first and second summer circuit coupled with double tail latch circuits and feedback paths, and omitting selection circuitry to reduce signal transmission delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory device operating speed increases, then data rate improves, but signal distortion and errors increase due to insufficient DFE correction speed
Solution Approach 1:
The DFE is divided into multiple independent tap circuits (first tap circuit, second tap circuit, etc.), each processing specific delay versions of the signal. This segmentation allows parallel processing of interference correction for different time delays, enabling the DFE to keep up with high data rates while maintaining signal accuracy.
Solution Approach 2:
The DFE performs preliminary correction of inter-symbol interference by generating corrected signals in advance using feedback from previously decoded data. The correction is applied before the current data bit is finalized, allowing the system to maintain high speed operation while ensuring reliable signal reconstruction.
2Reliability
If DFE correction is applied to correct inter-symbol interference, then signal accuracy improves, but transmission delay increases making correction insufficient for high-speed operation
Solution Approach 1:
The correction process is segmented into multiple parallel tap circuits, each handling a specific delay tap. This parallel segmentation eliminates sequential processing delays, allowing the DFE to provide accurate correction without adding significant transmission delay, thus enabling high-speed operation.
Solution Approach 2:
The DFE uses feedback from previously decoded and reliable data bits to generate correction signals for current data bits. This feedback mechanism allows the system to continuously adapt and correct interference in real-time, maintaining signal accuracy without introducing excessive delay that would compromise high-speed performance.
3Measurement precision
If multiple tap circuits are used to correct different delay components, then correction accuracy improves, but device complexity increases
Solution Approach 1:
The DFE is segmented into multiple tap circuits, where each tap circuit corresponds to a specific delay component. This segmentation enables precise correction of different interference components while maintaining a modular and systematic circuit architecture, making the complexity manageable and organized.
Solution Approach 2:
Each tap circuit in the DFE is designed with a universal structure that can handle multiple functions: signal delay, interference calculation, and correction output. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby controlling overall device complexity while maintaining high correction accuracy.
Data Source
AI summary
A device is provided that includes a decision feedback equalizer (DFE) with a first summer circuit and a second summer circuit. The DFE also includes a first double tail latch circuit coupled to the first summer circuit and a feedback path disposed between latches of the first double tail latch circuit and coupled to the second summer circuit to provide a tap signal to the second summer circuit. The DFE further includes another double tail latch circuit coupled to the second summer circuit and a feedback path disposed between latches of the second double tail latch circuit and coupled to the first summer circuit to provide a tap signal to the first summer circuit.