Memory Clock Duty Training with Parallel Data and Read Adjustment
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Solution Overview
Problem
Current clock training methods for memory devices, such as data and read clock training, are time-consuming and resource-intensive due to sequential and repetitive adjustments, which can lead to deviations in duty cycle and malfunction.
Innovation Solution
A memory device that performs parallel duty cycle training on both data and read clocks using a first and second duty cycle monitoring mechanism, calculating an offset and correcting duty errors to synchronize clocks, thereby reducing training time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sequential clock training methods are used for data and read clocks, then each clock can be trained individually, but the total training time is extended and system resources are consumed
Solution Approach 1:
The patent combines data clock training and read clock training into a single unified training process. The training circuit simultaneously performs duty cycle monitoring and adjustment for both clocks, merging what were previously separate sequential operations into one concurrent process, thereby reducing total training time while maintaining measurement precision
Solution Approach 2:
The training circuit continuously monitors and adjusts both data and read clocks in parallel without interruption. By maintaining continuous useful action on both clocks simultaneously rather than alternating between them, the training process achieves faster convergence and reduces overall training time
2Reliability
If repetitive sequential adjustments are performed on data and read clocks, then duty cycle can be corrected, but training process becomes time-consuming and resource-intensive
Solution Approach 1:
The patent merges the repetitive adjustment operations for data and read clocks into a single parallel process. The training circuit performs duty cycle monitoring and adjustment for both clocks simultaneously, eliminating the need for repetitive sequential adjustments and thereby improving training efficiency while maintaining clock synchronization reliability
Solution Approach 2:
The training circuit dynamically changes duty cycle parameters for both clocks in parallel based on real-time monitoring results. By adjusting duty cycle parameters simultaneously for data and read clocks rather than sequentially, the system achieves faster convergence to synchronized operation while maintaining reliability
Data Source
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AI summary
A memory device is provided which comprises a first signal pin configured to receive a data clock; a second signal pin configured to transmit a read clock; and a data clock circuit receiving the data clock and configured to perform first duty cycle monitoring that monitors a duty cycle of the data clock, generates a first result, and provides a timing-adjusted data clock in response to the first duty cycle monitoring; perform second duty cycle monitoring that monitors a duty cycle of the read clock, generates a second result, and provides a timing-adjusted read clock in response to the second duty cycle monitoring; calculate an offset of the read clock in response to the timing-adjusted data clock, the first result and the second result, and correct a duty error of the read clock using a read clock offset code derived in relation to the offset of the read clock.