Redundant Read Logic in Memory for Low-Power Access
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Solution Overview
Problem
Embedded memories contribute significantly to power consumption in system-on-a-chip (SoC) due to high power consumption during active modes, despite efforts to reduce power consumption during idle periods.
Innovation Solution
Implementing a single-port or dual-port redundant read memory system with logic circuits that compare current and preceding addresses to suppress redundant read operations, using multiplexers to control chip select or read enable signals, ensuring power-saving operations without slowing memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the memory power supply voltage is increased during active mode to enable high-speed memory operations, then memory operation speed is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by suppressing only the redundant read operations while allowing necessary read operations to proceed. The redundant read suppression logic detects when consecutive read operations access the same address and suppresses the second read, thereby partially reducing memory access activity and power consumption without completely disabling read operations, thus maintaining necessary memory performance
Solution Approach 2:
The patent implements periodic action through clocked control signals that periodically enable or disable read operations based on detected redundancy patterns. The redundant read suppression logic uses clocked registers and control signals to rhythmically gate memory access, creating periodic on/off cycles that reduce average power consumption while maintaining operational capability when needed
2Use of energy by moving object
If redundant read operations are suppressed to reduce power consumption, then power consumption is reduced, but memory access efficiency may deteriorate
Solution Approach 1:
The patent employs feedback through the redundant read suppression logic that continuously monitors memory access patterns, compares consecutive read addresses, and dynamically adjusts read operation suppression based on detected redundancy. This closed-loop feedback mechanism ensures that suppression decisions are based on actual access patterns, preventing unnecessary suppression of beneficial reads while eliminating redundant ones, thus maintaining access efficiency
Solution Approach 2:
The patent applies self-service by implementing self-awareness of access patterns within the memory system. The redundant read suppression logic automatically detects and eliminates its own redundant operations through address comparison, making the system self-optimizing without external intervention. This self-service capability allows the memory system to autonomously improve power efficiency while maintaining productivity
3Loss of information
If address comparison logic is added to detect redundant reads, then redundant read detection capability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the address comparison logic to serve multiple functions: comparing read addresses for redundancy detection, generating suppression control signals, and potentially interfacing with existing memory control logic. This multi-functional design allows the same logic circuitry to perform various tasks, reducing the need for separate dedicated circuits for each function and thereby limiting complexity growth
Solution Approach 2:
The patent uses intermediary elements such as control signals and logic gates that mediate between the address comparison function and the memory read operation. These intermediary components translate address match results into suppression decisions without requiring direct complex interaction between all system elements, thereby simplifying the overall device architecture while maintaining detection capability
Data Source
AI summary
A memory is provided with a redundant read logic circuit that detects whether a current read operation should proceed as a redundant or non-redundant read operation. In a redundant read operation, the memory does not assert a word line voltage nor does it enable any sense amplifiers. The data for a redundant read operation is thus not provided by the memory but instead is retrieved from a global input/output (GIO) memory circuit such as a GIO latch.