Clock Slew Adjustment Circuit for High-Skew Clock Generation

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Solution Overview

Problem

High slew of input clock signals in semiconductor memory devices leads to early reset and failure of internal clock generation, exacerbated by process variations, voltage, and temperature, causing disruptions in memory operations.

Innovation Solution

Incorporating a clock slew adjustment circuit that reduces the slew of input clock signals using a driving circuit to generate a second clock signal with improved slew, allowing parallel discharge paths through additional transistors, preventing early reset and ensuring consistent clock generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high slew input clock signals are used, then clock speed and operation efficiency are improved, but early reset and internal clock generation failure occur

Engineering Contradiction:

Improveclock speedVSAvoidinternal clock generation reliability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

A slew adjustment circuit is introduced as an intermediary component between the input clock signal and the internal clock generation circuit. This circuit reduces the slew rate of the input clock signal to a level that prevents early reset while maintaining the high-speed operation benefit, thus mediating between the conflicting requirements of speed and reliability

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The slew rate parameter of the input clock signal is dynamically adjusted through the slew adjustment circuit. By changing this physical parameter from high to an optimized level, the system achieves reliable internal clock generation while preserving the benefits of high-speed operation

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If process variations, voltage, and temperature changes occur, then manufacturing flexibility is improved, but clock signal integrity deteriorates

Engineering Contradiction:

Improvemanufacturing flexibilityVSAvoidclock signal integrity

Core Design Contradiction:

Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The slew adjustment circuit provides beforehand cushioning by pre-adjusting the input clock signal characteristics before they enter the internal clock generation circuit. This protective measure compensates for upcoming variations in process, voltage, and temperature, preventing these variations from degrading clock signal integrity

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The circuit incorporates feedback mechanisms that monitor the clock signal characteristics and adjust the slew rate accordingly. This feedback loop maintains clock signal integrity despite external variations by dynamically compensating for their effects

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20250321611A1Technique to Mitigate Clock Generation Failure at High Input Clock Skew

Publication Date: 2025.10.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Circuits and methods are provided for a clock generation circuit that includes a first transistor, wherein a gate of the first transistor is connected to a clock signal, a second transistor, connected in parallel to the first transistor, and a driving circuit, coupled to the second transistor, and comprising an input and an output, wherein the input of the driving circuit is connected to the clock signal, the output of the driving circuit is connected to a gate of the second transistor, and the driving circuit is configured to reduce a slew of the clock signal.