Memory Controller Data Training for Per-Line Duty Correction
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Solution Overview
Problem
In high-speed communication systems, signal integrity issues cause swing level deviations between data lines, making it difficult to correct duty errors and maintain signal integrity.
Innovation Solution
A memory controller with a training circuit and duty adjusters for each data line, which adjusts the duty of data based on target read reference voltages specific to each line, ensuring optimal signal characteristics across multiple data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed communication is performed through multiple data lines, then communication speed is improved, but swing level deviation between data lines increases due to signal integrity characteristics
Solution Approach 1:
The patent applies local quality by providing each data line with its own dedicated receiver and duty adjuster circuit. Each receiver is configured to receive data on a specific data line and compensate for that line's unique swing level deviation, rather than using a single shared compensation circuit. This localized approach allows each data line to be optimized independently for its specific signal integrity characteristics.
Solution Approach 2:
The patent changes the parameter of duty cycle for each data line based on measured swing level deviations. The duty adjuster modifies the duty cycle of the received data signal to compensate for signal integrity issues, transforming the parameter to achieve uniform signal characteristics across all data lines despite their physical variations.
2Device complexity
If duty correction is performed uniformly across all data lines, then device complexity is reduced, but duty error correction precision is insufficient due to varying physical characteristics of data lines
Solution Approach 1:
The patent implements local quality by configuring each data line with its own receiver and duty adjuster, allowing independent duty correction for each line based on its specific characteristics. This per-line configuration enables precise duty error correction that accounts for variations in physical characteristics such as trace length, impedance, and coupling effects.
Solution Approach 2:
The patent segments the duty correction function into separate duty adjuster circuits for each data line, rather than using a single unified correction mechanism. This segmentation allows each data line to receive customized duty correction tailored to its specific signal integrity profile, improving overall correction precision.
Data Source
AI summary
A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.