Multi-Voltage Cache Layout for Monolithic Logic Dies
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Solution Overview
Problem
The scaling of SRAM and logic circuits in semiconductor dies is hindered by increased area size due to interference among contacts, metal wire layouts, and parasitic junctions, leading to challenges in miniaturization and integration on a single monolithic die, particularly in AI chips, despite advancements in manufacturing technology.
Innovation Solution
A monolithic semiconductor die with multiple level caches operated at different voltages, utilizing a miniaturized transistor structure with direct M2 connections and self-aligned contacts, and optimized interconnection layers to reduce die size while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If SRAM and logic circuits are miniaturized on a monolithic die, then integration capacity increases, but area size increases due to interference among contacts, metal wire layouts, and parasitic junctions
Solution Approach 1:
The patent segments the cache memory into multiple levels (L1, L2, L3 caches) with different voltage domains. Each cache level operates at optimized voltage levels, allowing independent scaling and reducing interference between different circuit blocks. This segmentation enables higher integration capacity while managing die area by distributing functionality across voltage domains rather than uniformly miniaturizing all circuits.
Solution Approach 2:
The patent introduces voltage level as an additional dimension for organizing circuits. Instead of purely spatial arrangement, circuits are organized across multiple voltage levels (e.g., 1.0V for logic, 0.7V for L1 cache, 0.5V for L2 cache). This voltage stacking approach reduces parasitic effects and metal wire interference by separating circuits in the voltage domain, enabling higher integration without proportional area increase.
2Manufacturing precision
If technology nodes are shrunk to increase density, then manufacturing precision improves, but parasitic effects and interference increase
Solution Approach 1:
The patent changes the voltage parameter across different cache levels to optimize performance and reduce parasitic effects. Logic circuits operate at 1.0V while L1, L2, and L3 caches operate at progressively lower voltages (0.7V, 0.5V, 0.3V). This parameter change allows circuits to function at scaled dimensions without proportionally increasing parasitic effects, as lower voltage operation reduces electromagnetic interference and power consumption in miniaturized structures.
Solution Approach 2:
Different regions of the die are assigned different voltage qualities optimized for their specific function. Logic cores receive 1.0V for high-speed operation, while cache levels receive progressively lower voltages appropriate for their access patterns. This local quality assignment reduces parasitic coupling between high-speed logic and lower-speed cache, allowing tighter integration without exacerbating parasitic effects.
3Productivity
If multiple level caches are integrated on a single die, then performance increases, but device complexity increases
Solution Approach 1:
The patent implements dynamic voltage scaling across different cache levels. Each cache level can be independently powered and controlled, allowing the system to activate only the necessary cache levels based on workload requirements. This dynamic approach reduces effective complexity by disabling lower levels (e.g., L3) when only L1 is needed, while maintaining the performance benefit of having multiple levels available when required.
Solution Approach 2:
The voltage regulation infrastructure serves multiple functions: it powers different cache levels at appropriate voltages, provides isolation between voltage domains, and enables independent control of each cache level. This multi-functional approach reduces overall device complexity by using a single versatile voltage domain management system rather than separate control mechanisms for each cache level.
Data Source
AI summary
A monolithic die includes a substrate, a first processing logic unit within the substrate, a set of first low level caches within the substrate, and a first high level cache within the substrate; wherein the first processing logic unit is operated at a first operating voltage; each first low level cache is operated at a second operating voltage; the first high level cache is operated at a third operating voltage, and the second operating voltage is higher than the first operating voltage.