Shared CAP-RAM ADC Architecture for Lower Power and Area
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing CAP-RAM macro architectures for neural networks are power and area inefficient due to the large number of ADCs required, which limits their computational efficiency and form factor.
Innovation Solution
Implementing a shared ADC architecture where multiple CAP-RAM macros share a single ADC instance, reducing the number of ADCs needed and optimizing their usage through interleaved or sequential sampling methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If each CAP-RAM macro has its own dedicated ADC, then measurement precision and reliability are improved, but device complexity and area increase
Solution Approach 1:
Multiple CAP-RAM macros share a common ADC resource instead of each having a dedicated ADC. The ADC is time-multiplexed across different macros, where one macro undergoes ADC phase while others perform compute phases, and vice versa. This merging reduces the total number of ADC instances and overall device complexity.
Solution Approach 2:
The ADC is designed to serve multiple CAP-RAM macros universally through time-multiplexed operation. The same ADC hardware resource performs sampling functions for different macros at different time intervals, making the ADC multi-functional rather than dedicated to a single macro.
2Reliability
If each CAP-RAM macro has its own dedicated ADC, then reliability is improved, but power consumption increases
Solution Approach 1:
Multiple CAP-RAM macros share a common ADC resource instead of each having a dedicated ADC. The ADC is time-multiplexed across different macros, where one macro undergoes ADC phase while others perform compute phases, and vice versa. This merging reduces the total number of ADC instances and overall device complexity.
Solution Approach 2:
The ADC operates in periodic cycles, alternating between serving different CAP-RAM macros. During each cycle, one macro performs ADC phase while others perform compute phases, then they switch roles in subsequent cycles. This periodic time-multiplexed operation ensures reliable computational results while reducing total power consumption compared to having all ADCs operating simultaneously.
3Measurement precision
If more ADCs are used for each CAP-RAM macro, then measurement precision is improved, but area requirements increase
Solution Approach 1:
Multiple CAP-RAM macros share a common ADC resource instead of each having a dedicated ADC. The ADC is time-multiplexed across different macros, where one macro undergoes ADC phase while others perform compute phases, and vice versa. This merging reduces the total number of ADC instances and overall device complexity.
Solution Approach 2:
The system dynamically switches which macro is in ADC phase and which are in compute phase. This dynamic time-multiplexed allocation allows the same physical ADC hardware to serve multiple macros sequentially, effectively providing high measurement precision for each macro without requiring simultaneous dedicated ADC hardware for all macros, thus reducing total area.
Data Source
AI summary
A neural network architecture has a plurality of nodes, with each node being implemented in a CAP-RAM macro comprised of two or more rows of 6T-cell clusters. An analog voltage level present on each row can be sampled by an analog-to-digital converter (ADC) which sends a voltage value, in digital form, to a digital periphery. A first input to each of the ADCs is connected to an output line of a first CAP-RAM that is currently active, and a second ADC input is connected to an output of a second CAP-RAM that is in retention mode. Each ADC operates to sample an analog voltage level on an output line associate with the one CAP-RAM that is currently active.