Shared I/O Sub-Banks for More Memory Interfaces in Less Die Area
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Solution Overview
Problem
Integrated circuits (ICs) face limitations in the number of input/output (IO) banks due to size and floorplan constraints, restricting the ability to support multiple external memory interfaces within a single IO bank, leading to reduced flexibility and increased die size and cost.
Innovation Solution
Implementing IO banks with sub-banks that can be shared between multiple external interfaces, allowing each sub-bank to support different types of external devices, thereby increasing the number of supported interfaces and reducing die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If IO banks are increased to support multiple external memory interfaces, then the number of supported interfaces is improved, but the die size increases
Solution Approach 1:
The patent implements sub-bank sharing where a single IO bank can be dynamically allocated to support multiple different external memory interfaces (e.g., DDR3, DDR4, LPDDR4) through configurable interface logic. This multi-functionality allows one IO bank to replace what would traditionally require multiple dedicated IO banks, thereby supporting more interface types without proportionally increasing die size.
Solution Approach 2:
The IO bank is divided into sub-banks that can be independently configured and allocated to different external interfaces. This segmentation allows flexible resource allocation where sub-banks can be shared among multiple interfaces based on demand, optimizing the use of available IO resources without requiring additional die area for each interface.
2Reliability
If dedicated IO banks are allocated to each external interface, then interface reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic allocation of sub-banks to different external interfaces through configurable control logic. The IO bank can be dynamically reconfigured to support different interface types and configurations based on system requirements, maintaining reliability through proper resource allocation while avoiding the complexity of multiple static dedicated IO banks.
Solution Approach 2:
The patent introduces interface logic and control circuits as intermediaries that manage the shared IO bank resources. These intermediary components handle the complexity of interface configuration and allocation, isolating the complexity from the core IO bank structure while ensuring reliable interface support through standardized control mechanisms.
3Ease of manufacture
If the number of IO banks is reduced to decrease die size, then manufacturing cost is improved, but the number of supported external interfaces decreases
Solution Approach 1:
By designing IO banks with multi-functional sub-banks that can be configured to support different external memory interfaces, the patent reduces the total number of IO banks needed. This universality allows a smaller number of IO banks to perform the work of more dedicated banks, thereby reducing die size and manufacturing cost while maintaining support for multiple interface types.
Solution Approach 2:
The patent merges multiple interface support functions into shared IO banks with sub-bank allocation. Instead of having separate dedicated IO banks for each interface type, the functionality is merged into configurable shared resources, reducing overall die area and manufacturing complexity while preserving interface versatility.
Data Source
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AI summary
An integrated circuit includes a first input/output lane comprising first external terminals (101) and first driver circuits (111). The first driver circuits (111) exchange signals with a first external device through the first external terminals (101) as part of a first external interface. The first input/output lane is part of a sub-bank in an input/output bank (100) that implements at least a part of the first external interface. The integrated circuit includes a second input/output lane comprising second external terminals (102) and second driver circuits (112). The second driver circuits (112) exchange signals with a second external device through the second external terminals (102) as part of a second external interface. The second input/output lane is part of the sub-bank in the input/output bank (100) that implements at least a part of the second external interface.