Shared Holding Transistor Word-Line Driver Layout Reduction
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Solution Overview
Problem
The layout area of current word-line drive circuits is large due to the use of multiple holding transistors for each sub word line, leading to low integration of memory units.
Innovation Solution
A word-line drive circuit design where two sub word lines share a single holding transistor, allowing only one sub word line to be selected at a time, thereby reducing the layout area while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple holding transistors are used for each sub word line, then the reliability of sub word line control is improved, but the layout area of the word-line drive circuit increases
Solution Approach 1:
The patent merges the control functions of multiple holding transistors into a single shared holding transistor. Specifically, one holding transistor is used to control multiple sub word lines (e.g., WL0-WL7) through selective activation, reducing the total number of holding transistors from 8 to 1, thereby significantly reducing the layout area while maintaining control reliability through functional consolidation
Solution Approach 2:
The holding transistor is designed with multi-functionality to perform different control tasks for multiple sub word lines. By using control signals (e.g., WL0-WL7 control signals) to selectively activate the same holding transistor for different sub word lines, the circuit achieves universal control capability, reducing component count while maintaining the ability to reliably control each sub word line when needed
Data Source
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AI summary
A word-line drive circuit, a word-line driver and a storage device are provided. The word-line drive circuit includes at least two SWDs. Each SWD is connected to an MWL for providing an enable signal and a sub word line. The SWD includes a holding transistor. A first end and a second end of the holding transistor are respectively connected to different sub word lines, and a gate receives a second drive signal. The SWD is configured to provide a first drive signal to a selected sub word line in response to the first drive signal and the enable signal, the selected sub word line being a sub word line connected to the first end or second end of the holding transistor, and to conduct the first end and the second end of the holding transistor in response to the first drive signal, the enable signal and the second drive signal.