Clock Delay Scheduling for Data-Clock Skew Under Voltage Noise
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Solution Overview
Problem
Semiconductor memory devices face data capture malfunctions due to internal voltage noise and increased power consumption when capturing data in response to a DQS clock, especially under fluctuating power voltage conditions.
Innovation Solution
A clock circuit with a clock delay scheduler, first count logic circuit, and scheduler controller adjusts skew between data and clock signals by performing loop operations to identify and eliminate phase differences and slope changes in response to varying power voltage levels, using a sampler circuit to latch data and a duty corrector to amplify clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an internal voltage generation circuit is used to capture data in response to a DQS clock, then data capture reliability is improved by preventing external power noise interference, but internal voltage noise occurs and power consumption increases
Solution Approach 1:
The patent performs preliminary skew adjustment operations at different power voltage levels before actual data capture. The clock delay scheduler pre-calibrates the delay amount based on detected skew between data and clock signals, storing compensation values for different voltage conditions. This preliminary action ensures that when data capture occurs, the skew is already compensated, preventing capture failures without requiring continuous power-intensive voltage generation.
Solution Approach 2:
The patent dynamically adjusts the clock signal delay based on detected skew conditions. The clock delay scheduler modifies the delay amount according to the detected phase difference between data and clock signals, and according to the power voltage level. This dynamic adjustment optimizes the timing alignment adaptively, ensuring reliable data capture while minimizing unnecessary power consumption by only applying delay compensation when skew is detected.
2Productivity
If the frequency of a DQS clock is increased to meet high data transfer rate demands, then productivity is improved, but skew between data and clock signals increases causing capture malfunctions
Solution Approach 1:
The patent implements a feedback mechanism where the clock delay scheduler continuously detects the skew between data and clock signals and adjusts the clock delay accordingly. The system detects the phase difference, determines an appropriate delay amount, and applies compensation to align the clock with the data signals. This closed-loop feedback ensures that even at high frequencies where skew is more pronounced, the system maintains accurate data capture by continuously correcting timing misalignment.
3Reliability
If a clock delay scheduler is used to adjust skew between data and clock signals, then data capture reliability is improved, but device complexity increases due to additional loop operations
Solution Approach 1:
The patent segments the skew adjustment process into distinct operational loops: a first loop for detecting skew and determining delay amounts, and a second loop for applying delay compensation based on detected power voltage levels. By dividing the control function into separate modular loops with specific responsibilities, the system achieves reliable skew compensation while organizing the complexity into manageable, independent control blocks that can be implemented efficiently.
Data Source
AI summary
Provided are an apparatus and a method for adjusting a skew between data and a clock. The apparatus driven by a supply voltage includes a clock circuit that adjusts a skew between data and a clock. The clock circuit performs a first loop operation through a first loop and a second loop operation through a second loop, based on a phase difference between data and a clock. The first loop operation is performed until there is no phase difference between the data and the clock, and the second loop operation is performed until a first slope representing a change in delay of the data with respect to the levels of the power voltage and a second slope representing a change in delay of the clock become identical to each other.