Word Line Timing Control in Memory Circuits Under Voltage Swing
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines affects operating voltages and overall IC performance, necessitating a more flexible memory design.
Innovation Solution
Incorporating an adjustable delay circuit to control the timing of word line signals, allowing for delayed clock signals without reducing pulse width, thereby enhancing memory circuit flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor ICs are made smaller and more complex, then integration density increases, but conductive line resistance increases affecting operating voltages and performance
Solution Approach 1:
The patent implements dynamic voltage adjustment by delaying clock signals based on detected voltage conditions. The control circuit monitors operating voltages and selectively delays clock signals to compensate for voltage drops caused by high resistance in scaled-down conductive lines, thereby maintaining reliable operation in high-density integrated circuits
Solution Approach 2:
The patent changes the timing parameter of clock signals dynamically based on voltage conditions. By adjusting the clock signal delay time according to detected operating voltages, the system compensates for resistance effects in scaled conductive lines, allowing the circuit to adapt to varying voltage conditions in high-density implementations
2Adaptability or versatility
If clock signals are delayed to adjust timing, then timing flexibility improves, but pulse width may be reduced
Solution Approach 1:
The patent uses dynamic control to adjust only the timing edge of clock signals while preserving pulse width. The delay circuit selectively delays clock signal transitions based on control signals, allowing timing adjustment without reducing the duration of the clock pulse, thus maintaining both timing flexibility and adequate pulse width for reliable operation
Solution Approach 2:
The patent applies delay only to specific edges or portions of the clock signal rather than uniformly reducing the entire pulse. The control circuit targets specific timing parameters (rising/falling edges) for delay while maintaining the overall pulse width, providing localized timing adjustment without sacrificing pulse duration
Data Source
AI summary
A memory circuit includes a control circuit coupled to the word line driver circuit. The control circuit is configured to delay a leading or falling edge of a word line signal in response to at least a first clock signal. The control circuit includes a first clock circuit configured to generate a second clock signal in response to a first reset signal and a clock signal, and an adjustable delay circuit configured to adjust a delay between the second and third clock signal in response to the second clock signal and an enable signal. The third clock signal is a delayed version of the second clock signal. An amount of the delay between the second and third clock signal is based on a voltage difference between a first supply voltage having a first swing, and a second supply voltage having a second swing.