DDR PHY Floorplan Layout for Low-Jitter Routing and Power Gating
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Solution Overview
Problem
Existing DDR PHYs face challenges in reducing power consumption, increasing performance, and minimizing footprint area while meeting critical metrics such as clock jitter, wire-length, power gating, decoupling capacitance, and spatial variability, which are difficult to achieve with arbitrary floorplans.
Innovation Solution
A DDR PHY floorplan design that includes single-column I/O blocks, power switches adjacent to CA I/O subblocks, a centrally located PLL, and strategically placed decoupling capacitors to optimize clock routing, power distribution, and reduce footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data lanes are merged into a single differential pair for DQS signals, then routing complexity is reduced, but signal integrity deteriorates due to increased coupling with noisy data lanes
Solution Approach 1:
The patent segments the DQS signal routing by providing separate differential pairs for different signal types (DQS0-DQS3 for write, DQS4-DQS7 for read) rather than merging all data lanes into a single pair. This segmentation maintains signal integrity while organizing routing in a structured manner that reduces overall complexity.
Solution Approach 2:
The patent introduces dedicated buffer circuits (write DQS buffers and read DQS buffers) as intermediary components between the memory array and the external interface. These buffers act as mediators that condition and isolate the DQS signals, preventing direct coupling with noisy data lanes while maintaining signal integrity.
2Device complexity
If DQS signals are routed through the same differential pair as data lanes, then device complexity is reduced, but electromagnetic interference increases affecting signal quality
Solution Approach 1:
The patent segments electromagnetic signal paths by providing physically separate differential pairs for different signal functions. Write DQS signals use one set of differential pairs while read DQS signals use another set, preventing electromagnetic interference between different signal types and reducing overall EMI.
Solution Approach 2:
Dedicated buffer circuits are introduced as intermediary components that condition DQS signals before they reach the external interface. These buffers provide electrical isolation and signal conditioning, reducing electromagnetic interference with data lanes while maintaining signal integrity.
3Reliability
If separate differential pairs are provided for read and write DQS signals, then signal integrity is maintained, but device complexity increases
Solution Approach 1:
The patent segments DQS signal paths into dedicated differential pairs for read operations and separate differential pairs for write operations. This segmentation maintains signal integrity by preventing interference between read and write signals, while the structured organization keeps complexity manageable.
Solution Approach 2:
The patent employs universal buffer circuit designs that can handle both read and write DQS signals through separate instances. The same buffer architecture is used for both read DQS buffers and write DQS buffers, providing a scalable solution that maintains signal integrity while controlling complexity through design reuse.
Data Source
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AI summary
A double data rate (DDR) physical (PHY) provides an interface between a memory controller and a dynamic random-access memory (DRAM). The DDR PHY includes a first set of core logic configured to convert data between a single data rate and a double data rate, and a first data I/O block on a first side of the first set of core logic. The first data I/O block interfaces with the first set of core logic and the DRAM. The DDR PHY further includes a second set of core logic configured to process CA information, and a first CA I/O subblock on a second side of the first set of core logic. The first CA I/O subblock interfaces with the second set of core logic and the DRAM. The DDR PHY further includes a first set of power switches adjacent at least one side of the first CA I/O subblock. The first set of power switches is coupled to the first set of core logic and the second set of core logic.