Complementary Delay Circuits for Compact Memory Timing Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in maximizing operation efficiency while minimizing the area occupied by delay circuits, which are essential for controlling the timing of operations within a set time frame.
Innovation Solution
Incorporating complementary delay circuits that adjust their delay amounts based on a common bias, comprising a first delay circuit with a decreasing delay and a second delay circuit with an increasing delay, to generate control signals that synchronize internal operations within a target time frame.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple independent delay circuits are designed to control timing of operations, then operation timing control is achieved, but the area occupied by delay circuits increases
Solution Approach 1:
The patent merges multiple delay circuits into a unified delay control system where a single delay circuit generates multiple delay control signals for different operations. This consolidation reduces the total area occupied by delay circuits while maintaining the ability to control timing of various operations such as word line driving and sense amplifying operations.
Solution Approach 2:
The delay circuit is designed to serve multiple functions by generating different delay control signals for various operations within the memory device. A single delay circuit structure is configured to provide timing control for both row control circuit operations and sense amplifying circuit operations, making the delay circuit multi-functional and reducing overall area requirements.
2Area of stationary object
If delay circuits are minimized to reduce area, then area efficiency improves, but operation efficiency may be compromised
Solution Approach 1:
The delay circuit is designed with dynamic delay adjustment capability, allowing the delay amount to be varied based on operational requirements. This dynamic configuration enables the minimized delay circuit to still provide appropriate timing control for different operations, maintaining operation efficiency despite the reduced area footprint.
Solution Approach 2:
The delay circuit parameters are optimized and adjusted to achieve the required delay control functionality within a minimized area. By carefully tuning the delay circuit parameters and configuration, the patent ensures that timing control for critical operations such as word line activation and sense amplifying operations is maintained even with a compact delay circuit design.
Data Source
AI summary
A semiconductor device includes a first delay circuit having a first delay amount that decreases according to a common bias, and configured to generate a first delay control signal based on the first delay amount; a second delay circuit having a second delay amount that increases according to the common bias, and configured to generate a second delay control signal based on the second delay amount; a signal generation circuit configured to generate a plurality of internal control signals in response to at least one of the first delay control signal and the second delay control signal; and an internal operation circuit configured to complementarily perform a first operation and a second operation within a target time in response to the internal control signals.