Three-Stage Link Receiver Circuit for High-Speed Memory Interfaces
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Solution Overview
Problem
Current storage device designs face scalability issues due to low bandwidth and high load, which degrade performance at high speeds, particularly in client storage devices, and are not scalable to meet varying requirements across different categories such as client, enterprise, and RPG storage devices.
Innovation Solution
A receiver circuitry with a three-stage design, including a complementary amplifier, an equalizer, and a skew balanced level down shifter, to enhance gain and correct duty cycle errors, allowing operation across different categories of storage devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single stage complementary input receiver with thick oxide devices is used, then the receiver can operate at lower speeds with simpler architecture, but the bandwidth is limited and performance degrades at high speeds up to 2400 mbps
Solution Approach 1:
The receiver is divided into multiple stages: a first stage amplifier with thick oxide devices for robust operation, a second stage amplifier with thin oxide devices for high-speed performance, and intermediate circuitry. This segmentation allows each stage to be optimized for its specific function, enabling the overall receiver to achieve 2400 mbps while maintaining manageable complexity.
Solution Approach 2:
The invention changes the oxide thickness parameter between stages - using thick oxide devices in the first stage for stability and thin oxide devices in the second stage for high-frequency performance. This parameter change enables the receiver to maintain low complexity while achieving high speed operation by matching device characteristics to operational requirements.
2Speed
If the receiver architecture is scaled for high speeds, then higher data rates can be supported, but more loads are produced on the output lines causing performance degradation
Solution Approach 1:
Different regions of the receiver have different device characteristics - the first stage uses thick oxide devices with lower transconductance suitable for initial amplification, while the second stage uses thin oxide devices with higher transconductance optimized for driving output lines at high speeds. This local quality differentiation reduces output loading effects while maintaining high speed performance.
3Device complexity
If a self-bias approach is used in the receiver architecture, then the design is simpler, but higher speeds produce higher supply noise
Solution Approach 1:
The invention introduces an intermediate biasing stage between the first and second amplifiers that acts as a mediator. This intermediate circuit provides stable biasing for the high-speed second stage while isolating it from supply noise, and simultaneously protects the first stage from noise generated by the second stage. This resolves the contradiction by adding a moderate complexity element that effectively blocks noise propagation.
4Device complexity
If thick oxide devices are used in the level down shifter, then the design is simpler, but the bandwidth is limited and overall receiver penalty increases to approximately 80 ps at 1200 mbps
Solution Approach 1:
The level down shifter uses thin oxide devices instead of thick oxide devices, changing the critical parameter of oxide thickness. This parameter change increases the bandwidth and reduces the receiver penalty from 80 ps to approximately 20 ps at 1200 mbps, while the added complexity is offset by the performance gains in subsequent high-speed operation.
5Speed
If the receiver is designed for client storage devices with high data rates, then 2400 mbps can be supported, but the architecture becomes less scalable to other storage device categories with different requirements
Solution Approach 1:
The receiver architecture is designed with dynamic characteristics - the multi-stage structure with different oxide thicknesses can be selectively activated or configured based on operational requirements. The first stage with thick oxide devices provides robust operation for lower speeds, while the second stage with thin oxide devices enables high-speed operation, allowing the same architecture to adapt to different storage device categories through operational mode selection rather than structural redesign.
Data Source
AI summary
A receiver circuitry in a storage device may operate in stages. An amplifier in a first stage may receive an input and produce a high gain for all speeds with gain booster cells and a complementary input folded cascade structure. An equalizer including a resistor and a capacitor may increase the gain at high speeds in a second stage. In a third stage, a level down shifter may correct a duty cycle error resulting from shifting a signal across domain. The receiver circuitry may thus be used in different categories of storage devices with varying requirements.