3D Stackable Resistive Memory With Diodes Against Write Disturb
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Solution Overview
Problem
Current semiconductor technologies face challenges in achieving high integration density and preventing write disturb issues in memory cells during write operations due to leakage currents.
Innovation Solution
A 3D memory array with a 1T2R configuration is developed, featuring BEOL-compatible diodes and a staircase contact structure, which prevents leakage currents by electrically connecting diodes to resistors and using a multi-layer stack to reduce height and increase device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional semiconductor fabrication methods are used to increase integration density by reducing minimum feature size, then more components can be integrated into a given area, but write disturb issues and leakage currents increase in memory cells
Solution Approach 1:
The patent transitions from planar 2D memory cell layouts to a 3D vertical stack configuration. Multiple memory cells are stacked vertically along the Z-axis, with alternating N-type and P-type selective isolation regions providing electrical isolation between adjacent cells in the stack. This vertical stacking enables higher integration density while the isolation regions prevent leakage currents by creating distinct electrical pathways for each memory cell.
Solution Approach 2:
The memory array is segmented into multiple independently isolated memory cells arranged in a grid pattern with word lines and bit lines. Each memory cell is electrically isolated from its neighbors by N-type and P-type selective isolation regions. This segmentation allows individual cell control and prevents cross-talk and leakage between adjacent cells, enabling high-density integration without write disturb issues.
2Quantity of substance
If 3D vertical stacking is implemented to increase device density, then integration density improves, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple functions into shared structures: word lines extend horizontally to control multiple memory cells vertically stacked, bit lines provide column-wise access, and N-type/P-type selective isolation regions simultaneously provide electrical isolation and structural support. This merging reduces the number of independent components needed and simplifies the overall manufacturing process compared to fully independent 3D structures.
Solution Approach 2:
The horizontal word lines serve multiple functions: they control memory cells across different columns, provide electrical connectivity to multiple stacked cells, and act as a reference for vertical alignment during fabrication. Similarly, the N-type and P-type isolation regions provide both electrical isolation and mechanical structural framework. This multi-functionality reduces manufacturing steps while achieving high device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents write disturb issues and increases memory density by reducing leakage currents and enhancing integration density through the use of diodes and a staircase contact structure in the 3D memory array.
Implementation Method 1
forming a first diode over and electrically connected to a first resistor of the memory cell and a second diode over and electrically connected to a second resistor of the memory cell
Data Source
AI summary
Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.