Three dimensional semiconductor device stack, system having the same, and method of operating three dimensional semiconductor device stack
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Solution Overview
Problem
Conventional three dimensional semiconductor device stacks face challenges in fabricating high-density memory devices due to increased layer counts, warpage, stress imbalance, and high resistances of word lines, which complicate manufacturing and increase yield loss.
Innovation Solution
A three dimensional semiconductor device stack design with symmetric non-volatile memory array devices and a non-volatile memory peripheral device that reduces layer count, optimizes signal and power transmission, and incorporates a z-direction switch for parallel operation, thereby enhancing storage density and reducing fabricating time and resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers is increased to achieve high-density memory, then storage capacity is improved, but manufacturing complexity and warpage increase
Solution Approach 1:
The memory device is divided into two separate non-volatile memory array devices (first and second NVMADs) with symmetric layer structures. Each NVMAD has a reduced layer count compared to a single high-density device, making manufacturing more manageable while achieving high total storage capacity through the combination of both devices.
Solution Approach 2:
The patent transitions from a single-plane memory structure to a multi-plane three-dimensional stack structure. Multiple planes are stacked vertically with functional devices positioned between them, enabling high storage density in the vertical dimension rather than expanding horizontally with increasing layer counts in a single device.
2Quantity of substance
If more word lines are added to increase memory capacity, then storage density is improved, but word line resistance increases
Solution Approach 1:
The word lines are segmented and distributed across two separate non-volatile memory array devices. Each device has its own set of word lines with reduced resistance, rather than having all word lines in a single high-resistance structure. The functional devices positioned between the NVMADs provide optimized electrical connections.
Solution Approach 2:
Functional devices are positioned between the first and second non-volatile memory array devices to serve as intermediary connection points. These functional devices include switching elements that optimize the electrical pathways and reduce overall resistance for word line connections across the three-dimensional stack.
3Ease of operation
If asymmetric layout is used to optimize functionality, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
While the overall structure uses symmetric layouts for manufacturing ease, asymmetric functional elements are strategically positioned within the symmetric framework. The functional devices are placed between the two symmetric NVMADs, creating an asymmetric functional distribution that optimizes performance while maintaining symmetric manufacturable structures.
Solution Approach 2:
The patent applies different qualities to different regions: the NVMADs have symmetric layouts for manufacturing precision, while the functional devices positioned between them provide localized asymmetric functionality for optimized performance. This local differentiation allows both manufacturing ease and device performance to be achieved.
Data Source
AI summary
A three dimensional semiconductor device stack includes a first non-volatile memory array device, a second non-volatile memory array device, and a functional device. The first non-volatile memory array device includes a plurality of planes. The second non-volatile memory array device included a plurality of planes. The functional device is electrically connecting to the first non-volatile memory array device and the second non-volatile memory array device. The functional device includes a z-direction switch and a plane switch. The z-direction switch is configured to select one of the first non-volatile memory array device and the second non-volatile memory array device, and the plane switch is configured to select one of the planes of the selected first non-volatile memory array device or the selected second non-volatile memory array device. A method of operating the three dimensional semiconductor device stack is also disclosed.