3D Metal Stack Vertical Channels for Higher Transistor Density
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in scaling transistor density beyond single-digit nanometer nodes, as 2D circuits reach their limits, necessitating the development of 3D integration methods to increase transistor density in volume rather than area.
Innovation Solution
The method involves forming a multilayer stack with alternate metal and dielectric layers, creating vertical channel structures by epitaxial growth, and using self-aligned metal connections to enhance 3D transistor stacking, enabling increased packing density and performance through close proximity and alignment of metal connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D circuit scaling is continued to increase transistor density, then transistor density per unit area increases, but manufacturing precision and electrostatic device limitations prevent further scaling at single-digit nanometer nodes
Solution Approach 1:
The patent transitions from 2D planar circuits to 3D vertical stacking by forming multiple transistor layers stacked vertically on the substrate. This dimensional change allows transistor density to increase in the vertical direction rather than being constrained by horizontal scaling limits, thereby resolving the contradiction between increasing transistor density and manufacturing precision limitations at single-digit nanometer nodes.
2Quantity of substance
If 3D integration is implemented to increase transistor density in volume, then transistor density increases beyond 2D limits, but device complexity and fabrication process difficulty increase
Solution Approach 1:
The patent divides the 3D integration into discrete nanoplane dielectric layer stacks that can be independently formed and then thermally bonded together. Each nanoplane stack is a segmented unit containing metal layers and dielectric layers, which simplifies the overall fabrication process by breaking down the complex 3D structure into manageable repeating units that can be manufactured and assembled systematically.
Solution Approach 2:
The patent performs preliminary formation of complete nanoplane dielectric layer stacks on separate substrates before thermal bonding. The metal layers, dielectric layers, and vertical channel structures are all pre-formed in their final configurations on individual nanoplane stacks, which then undergo thermal bonding to create the integrated 3D device. This preliminary action reduces fabrication complexity by allowing each nanoplane to be independently optimized and prepared.
3Quantity of substance
If thermal bonding of nanoplane dielectric layer stacks is used to form combined dielectric layer stack, then transistor density increases through 3D stacking, but manufacturing process complexity increases
Solution Approach 1:
The patent employs self-aligned formation processes where the metal layers and dielectric layers are automatically positioned relative to each other through the sequential deposition and etching steps. The vertical channel structures are formed to be self-aligned with the metal layers, eliminating the need for additional alignment steps during thermal bonding. This self-service approach simplifies the manufacturing process by reducing the complexity of precise alignment requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-performance 3D transistor stacking with increased packing density and speed performance, facilitating the formation of N-type and P-type devices with optimized source, drain, and gate electrodes within an initial layer stack, addressing the limitations of 2D scaling.
Implementation Method 1
forming a multilayer stack on a substrate. The multilayer stack can include alternate metal layers and dielectric layers
Implementation Method 2
forming a multilayer stack on a substrate. The multilayer stack can include alternate metal layers and dielectric layers
Implementation Method 3
forming a first vertical channel structure within the first opening, and forming a second vertical channel structure within the second opening
Data Source
AI summary
Aspects of the present disclosure provide a method of fabricating a semiconductor device. For example, the method can include providing a substrate. The substrate can include a first type region and a second type region. The method can also include forming a multilayer stack on the substrate. The multilayer stack can include alternate metal layers and dielectric layers. The method can also include forming first and second openings through the multilayer stack to uncover the first and second type regions, respectively. The method can also include forming first and second vertical channel structures within the first and second openings, respectively. Each of the first and second vertical channel structures can have source, gate and drain regions being in contact with vertical sidewalls of the metal layers of the multilayer stack uncovered by a respective one of the first and second openings.