3D Microelectronic Package with Embedded Cooling Channels
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Solution Overview
Problem
Three-dimensional (3D) microelectronic chip packages face increased thermal resistance and temperature due to stacking, as conventional cooling mechanisms become insufficient for high-power chip stacks, and integrating cooling channels while maintaining electrical connections has not been practically achieved.
Innovation Solution
The implementation of 3D microelectronic chip packages with embedded cooling channels, where silicon chips have coolant channels interspersed between thru-silicon vias (TSVs) and capped with silicon caps that include inlet and outlet holes for fluidic couplings, allowing for the introduction and removal of coolant fluid, while maintaining electrical connections through TSVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chips are stacked vertically to reduce footprint and improve performance, then device density and performance are improved, but thermal resistance increases and temperature rises
Solution Approach 1:
The patent segments the cooling function by introducing separate coolant channels within the chip stack, dividing the thermal management task into dedicated fluid pathways that traverse through individual chips and interconnect layers, allowing independent cooling optimization for each chip layer
Solution Approach 2:
The patent transitions from two-dimensional planar cooling to three-dimensional vertical cooling by embedding coolant channels that extend through the stacked chip structure in the vertical dimension, enabling heat removal from multiple chips simultaneously through the depth of the stack
2Device complexity
If conventional conduction cooling is used for high-power chip stacks, then device complexity is low, but cooling effectiveness becomes insufficient
Solution Approach 1:
The patent applies hydraulic cooling by introducing liquid coolant flowing through embedded channels within the chip stack, using fluid dynamics to efficiently remove heat from high-power chips where conduction cooling alone is insufficient
Solution Approach 2:
The patent merges the electrical interconnect structure with the cooling channel structure by integrating coolant pathways within the same physical envelope as the electrical interlayers, allowing dual functionality of structural support and thermal management
3Temperature
If cooling channels are introduced into the chip stack, then thermal management is improved, but maintaining electrical connections becomes difficult
Solution Approach 1:
The patent segments the chip stack into distinct functional layers with coolant channels embedded in non-conductive interconnect layers, separating the cooling function from electrical signal paths to maintain electrical integrity while providing thermal management
Solution Approach 2:
The patent uses non-conductive interconnect layers as intermediaries that contain the coolant channels, acting as a mediator that enables thermal management through fluid flow while maintaining electrical isolation and connection between chip layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively introduces cooling channels within the 3D chip stack, enhancing thermal management and maintaining electrical connectivity, thereby reducing chip temperature and improving performance in high-power chip stacks.
Implementation Method 1
The first silicon chip comprises first coolant channels interspersed between first thru-silicon-vias (TSVs)... providing for introducing coolant fluid into the first coolant channels and removing the coolant fluid from the first coolant channels
Data Source
AI summary
The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.