3D Microelectronic Assembly for Dense Die Interconnects
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Solution Overview
Problem
Current techniques for coupling integrated circuit devices are limited by manufacturing constraints, device size, thermal considerations, and interconnect congestion, which impact costs and implementations, particularly in achieving reliable signal communication and power delivery between small, densely packed dies.
Innovation Solution
The implementation of a microelectronic assembly that includes a first die and a second die with conductive contacts on both faces, connected via die-to-die interconnects and a redistribution layer, allowing for direct power delivery and improved signal speed while reducing package size, and enabling heterogeneous technology integration and mixed node integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If current coupling techniques are used for integrated circuit devices, then manufacturing is simplified, but device size cannot be reduced further and interconnect congestion occurs
Solution Approach 1:
The patent transitions from planar (2D) interconnect routing to three-dimensional (3D) vertical stacking with through-silicon vias (TSVs). This dimensional change allows signals to route vertically through the substrate rather than laterally across the surface, eliminating interconnect congestion while enabling smaller package footprints. Multiple dies are stacked in the vertical dimension, creating a 3D integration architecture that resolves the contradiction between compact size and routing capacity.
Solution Approach 2:
The patent divides the integrated circuit into multiple separate dies that are stacked and interconnected vertically. Each die can be independently manufactured and optimized, then assembled into a compact 3D package. This segmentation allows high-density interconnection without lateral routing congestion, as each die has dedicated vertical TSV connections to adjacent dies, resolving the interconnect congestion problem while achieving small package size.
2Volume of moving object
If dies are densely packed to reduce package size, then volume is reduced, but thermal management becomes difficult
Solution Approach 1:
The patent introduces an intermediary substrate or interposer layer between the stacked dies that serves as a thermal management interface. This intermediary structure provides dedicated thermal vias and heat dissipation pathways that conduct heat vertically away from the densely packed dies. The intermediary layer acts as a thermal conduit, allowing high-density stacking while maintaining effective heat removal, thus resolving the contradiction between compact volume and thermal management.
3Use of energy by moving object
If conventional interconnect methods are used, then manufacturing is straightforward, but power delivery efficiency is limited
Solution Approach 1:
The patent implements power delivery in the vertical dimension using through-silicon vias (TSVs) that conduct power directly between stacked dies. This 3D power routing eliminates long lateral power traces, reducing resistive losses and improving power delivery efficiency. The vertical TSV architecture provides direct, short-current paths for power distribution, achieving high efficiency despite increased manufacturing complexity from the additional fabrication steps required for TSV formation.
Data Source
AI summary
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.