3D MIM Capacitor Multilevel Plate Structure
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Solution Overview
Problem
Conventional Metal-Insulator-Metal (MIM) capacitors in IC devices have limitations in capacitance density, which restricts the reduction of semiconductor chip area and fails to meet the increasing demand for higher precision and smaller dimensions.
Innovation Solution
A three-dimensional (3D) MIM capacitor structure with a multilevel bottom capacitor plate and high-k dielectric layers, including silicon nitride with low hydrogen concentration, is introduced to increase capacitance per unit area, utilizing techniques like chemical vapor deposition and plasma enhanced CVD for dielectric layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar MIM capacitor structure is used, then manufacturing process is simple, but capacitance density is low
Solution Approach 1:
The patent transitions from a conventional planar (2D) MIM capacitor structure to a three-dimensional structure by adding vertical stacking of capacitor plates. The bottom capacitor plate is formed with multiple levels (first level and second level) that extend vertically, creating additional capacitance storage volume without increasing the horizontal chip area. This dimensional change enables capacitance density to increase from typical planar values to over 1 fF/μm2, directly resolving the contradiction between simple manufacturing and high capacitance density.
2Area of moving object
If device dimensions are scaled down, then chip area is reduced, but capacitance density must increase to maintain performance
Solution Approach 1:
By implementing vertical stacking of capacitor plates with multiple levels, the patent achieves high capacitance density within a reduced chip footprint. The multilevel bottom capacitor plate structure utilizes the vertical dimension to pack more capacitance into the same horizontal area, enabling chip area reduction while maintaining or improving total capacitance performance.
Solution Approach 2:
The patent employs a nested structure where the bottom capacitor plate contains multiple levels (first level and second level) that are vertically stacked within each other. This nesting arrangement allows multiple capacitor elements to be integrated in a compact vertical space, effectively increasing capacitance density without proportionally increasing chip area.
3Measurement precision
If precision capacitor requirements are met (voltage linearity < ±1 ppm), then capacitance density must be > 1 fF/μm2, but conventional structures cannot achieve both
Solution Approach 1:
The patent achieves precise voltage linearity control (< ±1 ppm) by carefully selecting and optimizing the dielectric material properties, specifically using a dielectric layer with controlled hydrogen concentration to minimize voltage coefficients (β and α). Simultaneously, the three-dimensional multilevel structure provides the necessary capacitance density (> 1 fF/μm2) to meet precision analog circuit requirements, resolving the contradiction between precision and density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D MIM capacitor design achieves capacitance densities up to 20 times higher than conventional planar MIM capacitors, providing capacitance values of 1.5 fF/μm2 to 20 fF/μm2, enhancing voltage linearity and reducing chip area requirements.
Implementation Method 1
utilizing techniques like chemical vapor deposition and plasma enhanced CVD for dielectric layer formation
Implementation Method 2
utilizing techniques like chemical vapor deposition and plasma enhanced CVD for dielectric layer formation
Data Source
AI summary
An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.