3D MIM Capacitor Sidewall Coupling for Area Efficiency

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Solution Overview

Problem

Conventional MIM capacitors face challenges with high manufacturing costs, inefficient spatial density, and low breakdown voltage due to their two-dimensional structure and material limitations, particularly the high resistance of vias and direct contact of the insulator layer with copper, leading to performance constraints.

Innovation Solution

The development of a three-dimensional (3D) MIM capacitor design that includes a bottom conductor with both a horizontally-extending bottom plate and vertically-extending sidewall portions, with an insulator layer between the top conductor and both portions, enhancing capacitive coupling and area efficiency while using materials like copper and aluminum to improve breakdown voltage and reduce series resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If conventional 2D MIM capacitor structure is used, then manufacturing process is simple, but area efficiency is low and breakdown voltage is limited

Engineering Contradiction:
Improvearea efficiencyVSAvoidcapacitor structure complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent transitions from a conventional two-dimensional planar capacitor structure to a three-dimensional structure by adding vertically extending sidewall portions to the bottom conductor. This dimensional expansion increases the effective capacitive coupling area without proportionally increasing the footprint area, thereby improving area efficiency while managing structural complexity through systematic design.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If insulator layer is in direct contact with copper bottom plate, then manufacturing is simple, but breakdown voltage is low

Engineering Contradiction:
Improvebreakdown voltageVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent introduces an intermediate barrier layer between the copper bottom plate and the insulator layer. This barrier layer prevents direct contact, thereby increasing breakdown voltage and preventing copper diffusion. The addition of this intermediate layer is integrated into the manufacturing process without significantly complicating the overall fabrication sequence.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If top plate is made thin to fit within metal layers, then integration is improved, but series resistance increases

Engineering Contradiction:
Improveseries resistanceVSAvoidcapacitor structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent addresses the series resistance issue by extending the bottom conductor vertically with sidewall portions, thereby increasing the effective capacitive coupling area in the vertical dimension. This allows for improved electrical performance without requiring the top plate to be thicker, maintaining integration within the metal layer constraints while reducing series resistance through enhanced coupling geometry.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Reliability

If multiple vias are used to reduce resistance, then performance improves, but manufacturing cost and complexity increase

Engineering Contradiction:
ImproveresistanceVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the capacitive coupling function across multiple surfaces including the bottom plate, sidewall portions, and top plate. This segmentation of the capacitive area reduces the reliance on multiple high-resistance vias for electrical connection, as the enhanced distributed coupling area provides lower overall series resistance with fewer via connections required.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11715757B2Three-dimensional metal-insulator-metal (MIM) capacitor
Publication Date: 2023.08.01 MICROCHIP TECHNOLOGY INC
  • US11715757B2 patent drawing
  • US11715757B2 patent drawing
  • US11715757B2 patent drawing

AI summary

A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor may include a bottom conductor including a bottom plate portion (e.g., formed in a metal interconnect layer) and vertically-extending sidewall portions extending from the bottom plate portion. An insulator layer is formed on the bottom plate portion and the vertically extending sidewall portions of the bottom conductor. A top conductor is formed over the insulating layer, such that the top conductor is capacitively coupled to both the bottom plate portion and the vertically extending sidewall portions of the bottom conductor, to thereby define an increased area of capacitive coupling between the top and bottom conductors. The vertically extending sidewall portions of the bottom conductor may be formed in a single metal layer or by components of multiple metal layers.