3D MIM Capacitor With Stacked Vertical Studs for Higher Capacitance Density
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Solution Overview
Problem
Existing BEOL processes for forming MIMCAPs in integrated circuits face challenges in increasing capacitance density without occupying valuable semiconductor die surface area, causing routing congestion and trace length increases.
Innovation Solution
The development of three-dimensional (3D) metal-insulator-metal (MIM) capacitors with vertically stacked metal studs, oriented orthogonal to the semiconductor surface, which are closely spaced to achieve high capacitance density within the interconnect layers, utilizing cavity walls and dielectric layers to enhance capacitance without increasing horizontal area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If horizontal metal plates are used in BEOL processes, then capacitor area is increased to achieve higher capacitance, but routing congestion increases and trace lengths increase
Solution Approach 1:
The patent transitions from horizontal metal plates to vertical metal studs, changing the spatial dimension of capacitor formation. The metal studs extend vertically through via layers and inter-metal dielectric layers, utilizing the third dimension (depth) to achieve capacitance without increasing horizontal footprint, thereby reducing routing congestion and trace lengths.
2Area of stationary object
If vertical metal studs are stacked to increase capacitance density, then area occupied by capacitors is reduced, but manufacturing complexity increases
Solution Approach 1:
The capacitor structure is segmented into multiple vertical metal studs stacked through different via layers and inter-metal dielectric layers. Each stud is formed in a separate via layer, allowing independent formation and integration with the existing multi-layer interconnect structure. This segmentation enables high capacitance density while maintaining compatibility with standard BEOL manufacturing processes.
3Quantity of substance
If metal plates are formed on side walls of trenches, then capacitance is increased, but precious semiconductor die surface area is occupied
Solution Approach 1:
Instead of forming capacitors on the semiconductor die surface (2D plane), the patent forms vertical metal studs that extend through the interconnect layers in the vertical dimension. This approach achieves capacitance generation in the third dimension, preserving valuable die surface area for active transistor circuits while still providing the required capacitance through the vertical stacking of metal studs through via layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases capacitance density by vertically stacking metal studs, reducing the area occupied by capacitors in the interconnect layers and minimizing routing congestion, while maintaining a compact footprint.
Implementation Method 1
a dielectric layer disposed between the cavity walls of each cavity of the plurality of cavities of the top plate and the stud side walls of a corresponding center stud of the plurality of center studs
Data Source
AI summary
A three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) includes a plurality of center studs disposed within cavity walls of a plurality of cavities in a top plate. The center studs and the cavity walls are oriented orthogonal to a first metal layer and extend through a first via layer and a second metal layer. Each center stud includes a metal layer stud in the second metal layer stacked on a via layer stud in the first via layer. A dielectric layer is disposed between the center studs and the cavity walls of the plurality of cavities in the top plate. The center studs are coupled to a first electrode, and the top plate is coupled to a second electrode in the interconnect layers. In some examples, the center studs can form vertically oriented cylindrical capacitive elements positioned for high capacitance density.