3D MOSFET Gate Structure With Gap-Fill Width Control

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Solution Overview

Problem

As semiconductor devices are scaled down, the operating characteristics of metal oxide semiconductor field effect transistors (MOSFETs) deteriorate, necessitating improved fabrication methods to enhance reliability and electrical properties.

Innovation Solution

The semiconductor device incorporates a three-dimensional field effect transistor (FET) design with vertically stacked semiconductor patterns and a gate electrode structure that includes gap-fill patterns with controlled widths, ensuring optimal spacing and electrical connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If MOSFET sizes are scaled down to increase integration, then device density increases, but operating characteristics deteriorate

Engineering Contradiction:
Improvedevice integration densityVSAvoidoperating characteristics
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel patterns, allowing multiple channels to occupy the same footprint area. This dimensional change enables higher device density while maintaining adequate channel dimensions for acceptable operating characteristics.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The gate electrode is divided into multiple segmented metal patterns that are vertically stacked and spaced apart, with gap-fill patterns filling the spaces between them. This segmentation allows each metal pattern to be optimized independently while collectively forming a functional gate structure that maintains electrical control over the channel.

Inventive Principle:
Principle #1Segmentation

2Reliability

If vertically stacked semiconductor patterns are used to maintain operating characteristics, then device complexity increases

Engineering Contradiction:
Improveoperating characteristicsVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple gate metal patterns are merged into a single integrated gate electrode structure that functions as one unified component. The gap-fill patterns are merged with the metal patterns to form a cohesive gate structure, simplifying the overall device architecture despite the vertical stacking.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The gate electrode structure serves multiple functions simultaneously: the metal patterns provide electrical control, the gap-fill patterns provide structural support and electrical isolation, and the vertical stacking provides both density enhancement and electrical performance. This multi-functionality reduces the need for additional separate components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260068301A1Semiconductor device
Publication Date: 2026.03.05 SAMSUNG ELECTRONICS CO LTD
  • US20260068301A1 patent drawing
  • US20260068301A1 patent drawing
  • US20260068301A1 patent drawing

AI summary

A semiconductor device is provided. The semiconductor device includes: a first active pattern on a first active region of a substrate; a second active pattern on a second active region of the substrate, wherein the first active region is spaced apart from the second active region in a first direction; a first channel pattern that includes first semiconductor patterns that are spaced apart from each other and vertically stacked on the first active pattern; and a gate electrode on the first channel pattern. The gate electrode includes: first metal patterns on the first semiconductor patterns on the first active region; and a gap-fill pattern between the first metal patterns on the first active region. A maximum width in the first direction of the gap-fill pattern is less than a maximum width in the first direction of the first metal patterns.